DAC38RF86 datasheet(7/147 Pages) TI2

7 / 147 page

DAC38RF86, DAC38RF96

DAC38RF87, DAC38RF97

www.ti.com

SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017

Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97

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Pin Functions

I/O

DESCRIPTION

NAME

NO.

AGND

C11, C12, D11, E11,

F12, J12, K11, L11,

M11, M12, D12, L12

Analog ground.

ALARM

CMOS output for ALARM condition. Default polarity is active low, but can be changed to active high via

RESET_CONFIG alm_out_pol control bit.

AMUX0

Analog test pin for SerDes, Lane 0 to Lane 3. Can be left floating.

AMUX1

Analog test pin for SerDes, Lane 4 to Lane 7. Can be left floating.

ATEST

Analog test pin for DAC, references and PLL. Can be left floating.

CLKTX+

Divided output clock, internal 100 Ω differential termination, self-biased, positive terminal.

CLKTX-

Divided output clock, internal 100 Ω differential termination, self-biased, negative terminal.

DACCLK+

A10

Device clock, internal 100 Ω differential termination, self-biased, positive terminal.

DACCLK-

Device clock, internal 100 Ω differential termination, self-biased, negative terminal.

DACCLKSE

A12

Single ended device clock optional input. Can be left floating if not used. internal 50 Ω termination.

DGND

A2, B2, C2, D2, D6, E2,

E7, F2, F6, G2, G7, H6,

J7, K2, L2, L3, L4, L5,

Digital ground.

EXTIO

C10

Requires a 0.1 μF decoupling capacitor to AGND.

GPI0

Factory use only. User should GND.

GPI1

Factory use only. User should GND.

GPO0

Used for CMOS SYNC0\ signal.

GPIO1

Used for CMOS SYNC1\ signal.

IFORCE

Test pin for on chip parametrics. Can be left floating.

RBIAS

I/O

Full-scale output current bias. Change the full-scale output current through DACFS in register DACFS

(8.5.72). Expected to be 3.6 kΩ to GND for 40 mA full scale output.

RESET

Active low input for chip RESET, which resets all the programming registers to their default state. Internal

pull-up.

RX0+

CML SerDes interface lane 0 input, positive

RX0-

CML SerDes interface lane 0 input, negative

RX1+

CML SerDes interface lane 1 input, positive

RX1-

CML SerDes interface lane 1 input, negative

RX2+

CML SerDes interface lane 2 input, positive

RX2-

CML SerDes interface lane 2 input, negative

RX3+

CML SerDes interface lane 3 input, positive

RX3-

CML SerDes interface lane 3 input, negative

RX4+

CML SerDes interface lane 4 input, positive

RX4-

CML SerDes interface lane 4 input, negative

RX5+

CML SerDes interface lane 5 input, positive

RX5-

CML SerDes interface lane 5 input, negative

RX6+

CML SerDes interface lane 6 input, positive

RX6-

CML SerDes interface lane 6 input, negative

RX7+

CML SerDes interface lane 7 input, positive

RX7-

CML SerDes interface lane 7 input, negative

SCLK

Serial interface clock. Internal pull-down.

SDEN

Active low serial data enable, always an input to the DAC38RFxx. Internal pull-up.

SDIO

M10

I/O

Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional input 4-pin mode. Internal

pull-down.

SDO

Uni-directional serial interface data output in 4-pin mode. The SDO pin is tri-stated in 3-pin interface

mode (default).

SLEEP

Active high asynchronous hardware power-down input. Internal pull-down.

SYNC0+

Synchronization request to transmitter for JESD204B link 0, LVDS positive output.

SYNC0-

Synchronization request to transmitter for JESD204B link 0, LVDS negative output.

SYNC1+

Synchronization request to transmitter for JESD204B link 1, LVDS positive output.

SYNC1-

Synchronization request to transmitter for JESD204B link 1, LVDS negative output.

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