DAC38RF86 datasheet(68/147 Pages) TI2

68 / 147 page

DAC38RF86, DAC38RF96

DAC38RF87, DAC38RF97

SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017

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Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97

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2. No RESET Value: These are NORMAL registers, but the reset value cannot be specified. This could be

because the register has some read_only bits or some internal logic partially controls the bit values.

3. READ_ONLY (R): Registers that can only be read.

8.4.5.2 WRITE_TO_CLEAR (W0C)

These registers are just like NORMAL registers with one exception. They can be written and read, however,

when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until it is

written to ‘0’. This way interrupts will be captured and stay constant until cleared by the user.

8.5 Register Maps

Table 42. Register Summary

Address

Reset

Acronym

Section

General Configuration Registers (PAGE_SET[2:0] = 000)

0x00

0x5803

RESET_CONFIG

Chip Reset and Configuration

8.5.1

0x01

0x1800

IO_CONFIG

IO Configuration

8.5.2

0x02

0xFFFF

ALM_SD_MASK

Lane Signal Detect Alarm Mask

8.5.3

0x03

0xFFFF

ALM_CLK_MASK

Clock Alarms Mask

8.5.4

0x04

0x0000

ALM_SD_DET

SERDES Loss of Signal Detection Alarms

8.5.5

0x05

0x0000

ALM_SYSREF_DET

SYSREF Alignment Circuit Alarms

8.5.6

0x06

variable

TEMP_PLLVOLT

Temperature Sensor and PLL Loop Voltage

8.5.7

0x07-0x08

0x0000

Reserved

0x09

0x0000

PAGE_SET

Page Set

8.5.8

0x0A-0x77

0x0000

Reserved

0x78

0x0000

SYSREF_ALIGN_R

SYSERF Align to r1 and r3 Count

8.5.9

0x79

0x0000

SYSREF12_CNT

SYSREF Phase Count 1 and 2

8.5.10

0x7A

0x0000

SYSREF34_CNT

SYSREF Phase Count 3 and 4

8.5.11

0x7B-0x7E

0x0000

Reserved

0x7F

0x0008

VENDOR_VER

Vendor ID and Chip Version

8.5.12

Multi-DUC Configuration Registers (PAGE_SET[0] = 1 for multi-DUC1, PAGE_SET[1] = 1 for multi-DUC2)

0x0A

0x02B0

MULTIDUC_CFG1

Multi-DUC Configuration (PAP, Interpolation)

8.5.13

0x0B

0x0000

Reserved

0x0C

0x2402

MULTIDUC_CFG2

Multi-DUC Configuration (Mixers)

8.5.14

0x0D

0x8300

JESD_FIFO

JESD FIFO Control

8.5.15

0x0E

0x00FF

ALM_MASK1

Alarm Mask 1

8.5.16

0x0F

0x1F83

ALM_MASK2

Alarm Mask 2

8.5.17

0x10

0xFFFF

ALM_MASK3

Alarm Mask 3

8.5.18

0x11

0xFFFF

ALM_MASK4

Alarm Mask 4

8.5.19

0x12

0x0000

JESD_LN_SKEW

JESD Lane Skew

8.5.20

0x13-0x16

0x0000

Reserved

0x17

0x0000

CMIX

CMIX Configuration

8.5.21

0x18

0x0000

Reserved

0x19

0x0000

OUTSUM

Output Summation and Delay

8.5.22

0x1A-0x1B

0x0000

Reserved

0x1C

0x0000

PHASE_NCOAB

Phase offset for AB path NCO

8.5.23

0x1D

0x0000

PHASE_NCOCD

Phase offset for CD path NCO

8.5.24

0x1E-0x20

0x0000

FREQ_NCOAB

Frequency for AB path NCO

8.5.25

0x21-0x23

0x0000

FREQ_NCOCD

Frequency for CD path NCO

8.5.26

0x24

0x0010

SYSREF_CLKDIV

SYSREF Use for Clock Divider

8.5.27

0x25

0x7700

SERDES_CLK

Serdes Clock Control

8.5.28

0x26

0x0000

Reserved

0x27

0x1144

SYNCSEL1

Sync Source Selection

8.5.29

0x28

0x0000

SYNCSEL2

Sync Source Selection

8.5.30

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