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DAC38RF86 bảng dữ liệu(PDF) 20 Page - Texas Instruments

tên linh kiện DAC38RF86
Giải thích chi tiết về linh kiện  DAC38RFxx Dual-Channel, Single-Ended, 14-Bit, 6- and 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip GSM PLL
PDF  147 Pages
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nhà sản xuất  TI2 [Texas Instruments]
Trang chủ  https://www.ti.com
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DAC38RF86 bảng dữ liệu(HTML) 20 Page - Texas Instruments

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DAC38RF86, DAC38RF96
DAC38RF87, DAC38RF97
SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017
www.ti.com
Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
7.9 Timing Requirements
MIN
NOM
MAX
UNIT
DIGITAL INPUT TIMING SPECIFICATIONS
TIMING: SYSREF+/-
ts(SYSREF)
Setup time, SYSREF+/- valid to rising
edge of DACCLK+/-
SYSREF Capture assist disabled
50
ps
th(SYSREF)
Hold time, SYSREF+/- valid after rising
edge of DACCLK+/-
SYSREF Capture assist disabled
50
ps
TIMING: SERIAL PORT
ts(/SDEN)
Setup time, SDEN to rising edge of SCLK
20
ns
ts(SDIO)
Setup time, SDIO valid to rising edge of SCLK
10
ns
th(SDIO)
Hold time, SDIO valid after rising edge of SCLK
5
ns
t(SCLK)
Period of SCLK
temperature sensor read
1
µs
All other registers
100
ns
td(Data)
Data output delay after falling edge of SCLK
25
ns
tRESET
Minimum RESET pulse width
25
ns
ANALOG OUTPUT
ts(DAC)
Output settling time to 0.1%
1
ns
tr
Output rise time 10% to 90%
50
ns
tf
Output fall time 90% to 10%
50
ns
LATENCY
RX SerDes AnalogDelay
250
ps
DAC wake-up time
IOUT current settling to 1% of IOUTFS
from deep sleep
90
µs
DAC sleep time
IOUT current settling to less than 1% of
IOUTFS in deep sleep
90
µs



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