DAC38RF86 datasheet(65/147 Pages) TI2

65 / 147 page

Fmax

min

PFD CP

Fvco

Fixed

div x Mdiv

÷N

PFD and Charge

pump

Output

buffer

÷4

÷M

PLL_M(7-0)

PLL_N(4-0)

VCO

DAC CLK

DAC38RF86, DAC38RF96

DAC38RF87, DAC38RF97

www.ti.com

SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017

Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97

Submit Documentation Feedback

Device Functional Modes (continued)

Figure 57. Internal PLL/VCO Block Diagram

The two parallel VCOs are tuned to a target center frequency of 5.9 GHz (low VCO) in DAC38RF87 and

DAC38RF97. They are tuned to a target center frequency of 8.85 GHz (high VCO) in DAC38RF86 and

DAC38RF96. The field PLL_VCOSEL in register PLL_CONFIG2 (8.5.81)must always be set to 0 in

DAC38RF87/97 and always set to '1' in DAC38RF86/96/88/81. Also GSMPLL_ENA in register PLL_CONFIG2

must always be set to '1' in all devices to ensure the two identical VCOs are connected in parallel. The 7 bit VCO

tuning code in field PLL_VCO in register PLL_CONFIG2 is used to tune the VCO frequency in the range of 5.24

GHz to 6.72 GHz for the low VCO and 7.96 GHz to 9.0 GHz for the high VCO. For the low VCO the center VCO

frequency is achieved with PLL_VCO = 63decimal and for the high VCO the target VCO center frequency is also

achieved with PLL_VCO = 63decimal.

The supply current, and therefore; the analog signal amplitude in the VCO is controlled using the field

PLL_VCO_RDAC in register PLL_CONFIG1 (8.5.80). This control signal should be set 15decimal initially for 18 mA

supply current in the VCO and ~1.4 VPP single ended oscillation amplitude.

The PLL has no prescaler, so the DAC sample rate is the VCO frequency. In the PLL feedback path a fixed ÷ 4

frequency divider block receives the VCO output clock and divides its frequency by 4. The maximum operating

frequency of the phase-frequency detector (PFD) is approximately 550 MHz. The M (feedback) clock divider

takes the output clock signal from the fixed ÷4 block and divides it by a programmable ratio set by the 8-bit field

in field PLL_M_M1 in register PLL_CONFIG1 (8.5.80). The programmable division ratio range is ÷1 to ÷256, and

is the value of the 8 bit unsigned binary code + 1. Although it is possible to program the M divider to ÷1, ÷2 and

÷3, these values should not be used. As stated previously the PFD and CP have a finite maximum operating

frequency, which is the VCO frequency divided by the fixed divider ratio multiplied by the minimum allowable M

divider ratio.

(14)

The N (reference) divider determines the ratio between the input reference clock frequency and the PFD

operating frequency, and is set by the 5-bit field PLL_N_M1 in register CLK_PLL_CFG (8.5.79). The division ratio

range is ÷1 to ÷32, and is the value of the 5-bit unsigned binary code + 1.

DAC38RF86 bảng dữ liệu(PDF) 65 Page - Texas Instruments

DAC38RF86 bảng dữ liệu(HTML) 65 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL