SRC4382IPFBT datasheet(71/85 Pages) TI2

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CHANNEL STATUS AND USER DATA BUFFER MAPS

SRC4382

SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

SRF7

SRF6

SRF5

SRF4

SRF3

SRF2

SRF1

SRF0

SRI[4:0]

Integer Part of the Input-to-Output Sampling Ratio

SRF[10:0]

Fractional Part of the Input-to-Output Sampling Ratio

In order to properly read back the ratio, these registers must be read back in sequence, starting with register 0x32.

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

PAGE1

PAGE0

PAGE[1:0]

Page Selection

These bits are utilized to select one of three register pages for write and/or read access via the SPI or I2C serial host interface. The Page

Selection Register is present on every register page at address 0x7F, allowing movement between pages as necessary.

PAGE1

PAGE0

Page 0, Control and Status Registers (Default)

Page 1, DIR Channel Status and User Data Buffers

Page 2, DIT Channel Status and User Data Buffers

Page 3, Reserved

Table 5 through Table 8 show the buffer maps for the DIR and DIT channel status and user data buffers.

For Table 5, the channel status byte definitions are dependent on the transmission mode, either Professional or

Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode.

This is applicable for Table 5 and Table 6.

For Table 7, the channel status byte definitions are dependent on the transmission mode, either Professional or

Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. In

Professional mode, Byte 23 for each channel is reserved for CRC data, which is automatically calculated and

encoded by the DIT. There is no need to program Byte 23 for either channel in Professional mode.

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