SRC4382IPFBT datasheet(23/85 Pages) TI2

23 / 85 page

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Audio Serial

PortA

Audio Serial

PortB

Digital

Interface

Receiver(DIR)

Digital

Interface

Transmitter

(DIT)

Asynchronous

Sample Rate

Converter

(SRC)

TX+

SDINA

SDOUTA

LRCKA

BC A

SDINB

SDOUTB

LRCKB

BC B

CPM

CS or A0

CCLKorSCL

CDINor

CDOUT orSDA

INT

RST

Host

Interface

(SPIor I C)

and

Gene a

r l-

Purp s

o e

Outputs

Master

Cl ck

Distribution

MC K

RXCKI

FromRXCKO

AESOUT

RXCKO

LOCK

RX +

RDY

MU E

BLS

SY C

ControlandStatus

Registers

DIRCand U

DataBuffers

DITCand U

DataBuffers

SRC4382

Power

VDD18

DGND1

VDD33

DGND2

VIO

DGND3

VCC

AG D

BG D

InternallyTied

toSubstrate

RESET OPERATION

SRC4382

SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007

Figure 59 shows a simplified functional block diagram for the SRC4382. Additional details for each function block

will be covered in respective sections of this datasheet.

Figure 59. Functional Block Diagram

The SRC4382 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the

internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset

low pulse width must be a minimum of 500ns in length. The user should not attempt a write or read operation

using either the SPI or I2C port for at least 500

μs after the rising edge of RST. See Figure 60 for the reset timing

sequence of the SRC4382.

In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby

all registers and buffers are forced to their default settings. Refer to the Control Registers section for details

regarding the RESET bit function.

Upon reset initialization, all functional blocks of the SRC4382 default to the powered-down state, with the

exception of the SPI or I2C host interface and the corresponding control registers. The user may then program

the SRC4382 to the desired configuration, and then release the desired function blocks from the power-down

state utilizing the corresponding bits in control register 0x01.

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