SRC4382IPFBT datasheet(31/85 Pages) TI2

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RX+

ToReceiver

Inputand Bypass

Multiplexers

24k

VDD33

24k

DGND2

SRC4382

SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007

Figure 68. Differential Line Receiver Circuit

The outputs of the four line receivers are connected to two 1-of-4 data selectors: the receiver input multiplexer

and the bypass multiplexer. The input multiplexer selects one of the four line receiver outputs as the source for

the AES3-encoded data stream to be processed by the DIR core. The bypass multiplexer is utilized to route a

line receiver output to either the DIT line driver or CMOS buffered outputs, thereby bypassing all other internal

circuitry. The bypass function is useful for simple signal distribution and routing applications.

The DIR requires a reference clock, supplied by an external source applied at either the RXCKI (pin 13) or MCLK

(pin 25) clock inputs. PLL1 multiplies the reference clock to a higher rate, which is utilized as the oversampling

clock for the AES3 decoder. The decoder samples the AES3-encoded input stream in order to extract all of the

audio and status data. The decoded data stream is sent on to a de-multiplexer, where audio and status data are

separated for further processing and buffering. The pulse generator circuitry samples the encoded input data

stream and generates a clock that is 16 times the frame/sampling rate (or fS). The 16fS clock is then processed

by PLL2, which further multiplies the clock rate and provides low-pass filtering for jitter attenuation. The available

PLL2 output clock rates include 512fS, 256fS, and 128fS. The maximum available PLL2 output clock rate for a

given input sampling rate is estimated by internal logic and made available for readback via status register 0x13.

The output of PLL2 may be divided by a factor of two, four, or eight, or simply passed through to the recovered

master clock output, RXCKO (pin 12). The RXCKO clock is also be routed internally to other function blocks,

where it may be further divided to create left/right word and bit clocks. The RXCKO output may be disabled and

forced to a high-impedance state by means of a control register bit, allowing other tri-state buffered clocks to be

tied to the same external circuit node, if needed. By default, the RXCKO output (pin 12) is disabled and forced to

a high-impedance state.

Figure 69 illustrates the frequency response of PLL2. Jitter attenuation starts at approximately 50kHz. Peaking is

nominally 1dB, which is within the 2dB maximum allowed by the AES3 standard. The receiver jitter tolerance plot

for the DIR is illustrated in Figure 70, along with the required AES3 jitter tolerance template. The DIR jitter

tolerance satisfies the AES3 requirements, as well as the requirements set forth by the IEC60958-3 specification.

Figure 70 was captured using a full-scale 24-bit, two-channel, AES3-encoded input stream with a 48kHz frame

rate.

The decoded audio data, along with the internally-generated sync clocks, may be routed to other function blocks,

including Port A, Port B, the SRC, and/or the DIT. The decoded channel status and user data is buffered in the

corresponding Receiver Access (RA) data buffers, then transferred to the corresponding User Access (UA) data

buffers, where it may be read back through either the SPI or I2C serial host interface. The contents of the RA

buffers may also be transferred to the DIT UA data buffers; see Figure 65. The channel status and user data bits

may also be output serially through the general-purpose output pins, GPO[4:1]. Figure 71 illustrates the output

format for the GPO pins when used for this purpose, along with the DIR block start (BLS) and frame

synchronization (SYNC) clocks. The rising edges of the DIR SYNC clock output are aligned with the start of each

frame for the received AES3 data.

The DIR includes a dedicated, active low AES3 decoder and PLL2 lock output, named LOCK (pin 11). The lock

output is active only when both the AES3 decoder and PLL2 indicate a lock condition. Additional DIR status flags

may be output at the general-purpose output (GPO) pins, or accessed through the status registers via the SPI or

I2C host interface. Refer to the General-Purpose Digital Outputs and Control Registers sections for additional

information regarding the DIR status functions.

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