L9305 datasheet(35/107 Pages) STMICROELECTRONICS

35 / 107 page

High side fail safe pre-driver

For safety purpose the solenoid loads must be connected to battery line through an external fail safe switch driven

by L9305: in case of fault the device must be always able to disconnect external fail safe switch to avoid

unwanted energization of solenoid loads. The device provides also diagnostic for external switch, by means of

VDS comparator, to detect overcurrent/short conditions and prevent FET from overheating.

In PWSSO36 package, L9305 provides one fail safe pre-driver channel to control an external high side N-channel

safety switch. In TQFP48 package, L9305 provides 4 fail safe pre-driver channels to control 4 external high side

N-channel safety switches. The pre-driver protects the external N-channel Mosfet by monitoring the drain to

source voltage drop across the Mosfet. The threshold for this diagnostic is programmable by the user in the

FSCONF register, bits D[1:0]. To enable the output driver, set bit D[2]=1 in the FSCONF register. Upon enabling

the output driver, fault monitoring is masked for a period of T_FS_VDS_blank and filtered for T_FS_VDS_flt.

Should a fault be detected, the VDS fault flag is set in the SERVFLT1 register, bit D[10]. The fault bit is latched

and is clear on read. To re-enable the failsafe pre-driver, the fault must be cleared and the enable bit must be set

again through the SPI (FSCONF register).

An external microcontroller can inhibit pre-driver activation by means of the EN_DR input pin: if this pin is driven

low the failsafe gate is pulled to ground by an internal switch-off path parallel to the digital one. The internal switch

off path is triggered also in case of safety relevant internal faults such as stuck of main clock or overvoltage of the

logic core supply voltage.

While the device is in either IDLE or RUNNING mode, EN_DR is set high and FS_EN is set high through an SPI

command, the user can set EN_DR low and verify that the fail-safe switch is disabled thru the parallel safety

switch off path by reading the PINSTATUS register SAFETY echo (bit D[7]). The user can also verify the EN_DR

status reading the PINSTATUS register, bit D[0].

Figure 17. Fail safe concept

FS_CMD

FS_Dx

VBATP

VCP

FS_Gx

FS_Sx

IBIAS

IPU

IPD

VDS_fault

–

GADG2709181321PS

The Fail Safe pre-driver can be in the following states:

•

FS OFF: Device in Idle State. Fail Safe related registers at their default state. Internal reset state

•

FS IDLE: Fail safe disabled. Fail safe related registers preserved but Enable Low. Two cases:

–

EN_DR low. Echo on SPI

–

Error on FS present. Error on SPI and on FAULT pin, if not masked.

•

RUNNING: Fail Safe enabled and running with gate status depending on SPI command register value

L9305

High side fail safe pre-driver

DS12774 - Rev 10

page 35/107

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