L9305 datasheet(49/107 Pages) STMICROELECTRONICS

49 / 107 page

•

Input pins:

–

CS: Chip Select Active Low

–

SCLK: SPI Clock

–

MOSI: Master Output Slave Input. Communication path from MCU to the device

•

Output pins:

–

MISO: Master Input Slave Output. Communication path from the device to the MCU

9.2

CRC

Received and transmitted data are verified using a 5-bit CRC field. The CRC is calculated from D[31] of the frame

to D[5] excluding frame counter bit, D[21]. The CRC field is checked using 5° degree polynomial and is

implemented per the following equation:

g(x)= x5 + x2 + 1

If a CRC error is detected, the received frame is ignored and the fault is indicated in the next SPI frame.

In the logic block for CRC calculation, internal logic shift register is initialized all ‘1’: user should take this into

account when executing hand calculations for CRC check.

In fact, since internal logic shift register is initialized all ‘1’, most significant 5 bits must be complemented, in

addition, as already stated, Bit 21 must be removed and Bit 4 to Bit 0 must be removed for CRC calculation.

For example, in order to calculate CRC for data “0x1820080A”, user should consider the following data:

Data = "11100000000000000001000000";

which should be divided by 100101, then “01010” should result as a CRC.

As a double check that the remainder is 0, user has to concatenate the 01010 to the previous data and then

divide by 100101, i.e:

Data = "1110000000000000000100000001010";

and divide by 100101, then ‘0’ will be obtained as a remainder.

9.3

SPI errors management

If a communication fault is detected, the SPI error bit (MISO[31]: E bit) is set to “1” and the frame is ignored. The

SPI error bit always refers to the previous SPI frame. The next figure shows the SPI frame sequence for faulted

communications.

Figure 26. SPI frame with error on previous SPI frame

Frame #n with SPI protocol Error

Add_#n

Data[Add_#n] [not updated]

IC Registers

Data__#n = 0xABCD

crc

Data_#n-1

Add_#n-1

Frame #n+1

Add_#n+1

Data_#n+1 = 0xYYYY

crc

SPI Fault Flag Register

Comm. Fault Addr

GADG2709181500PS

9.4

SPI timeout monitoring function

An internal monitor detects a failure if the period between communications exceeds the SPI Timeout period. This

monitoring function detects loss of the communications between the microcontroller and the device.

If no valid frames are received before the Timeout Configuration period elapses, the SPI Timeout flag is set

(SERVFLT1 register, D[6]) and the FAULTn pin is set low if the corresponding fault mask bit is not set.

The Timeout Configuration value is programmable through a 3-bit SPI field (TIMEOUTSPICFG register, D[4:2])

with a default value of 2 ms. The timer is cleared when a valid SPI frame is received.

L9305

SPI

DS12774 - Rev 10

page 49/107

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