L9305 datasheet(45/107 Pages) STMICROELECTRONICS

45 / 107 page

The typical procedure for running the diagnostic comparator self-test is outlined below:

•

Disable off-state diagnostics, set CONFIGURATION1 register, D[5] = 0

•

Enable diagnostics self-test, CONFIGURATION2 register, D[1] = 1

•

Read results in EXCEPTIONS1 register, D[8:7]

8.4.6

PWM check

The L9305 can verify output driver status with respect to the PWM input signal. This function can only be

performed when the channel is enabled and controlling load current. Should a mismatch be detected, the PWM

Check Fault, D[12] is set in the EXCEPTIONS1 register.

8.4.7

Valve driver safety electrical characteristics

5.5 V ≤ VBATP ≤ 19 V; 5.5 V ≤ VSx ≤ 19 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise noticed. All voltages refer to

GNDA pin.

Table 33. Valve driver safety parameters

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

Delta_curr_sense

Tolerable mismatch between

high side and low side current

sense

Guaranteed by scan, Iload =

0.8 A

-15

–

LOAD_SOLx

ADC_checkHILOAD=0

Tolerable mismatch between

functional and safety ADCs

Guaranteed by scan

-128

–

128

ADC_checkHILOAD=1

Tolerable mismatch between

functional and safety ADCs

-170.6

–

170.6

t_ADC_blank

Self test blanking time

Guaranteed by scan

–

µs

t_BIST

Solenoid digital BIST duration

Guaranteed by scan

–

t_BIST

Analog BIST duration

Guaranteed by scan

0.9

1.7

1.8

t_EEPROM

EEPROM download time

Guaranteed by scan

–

t_PWM_check

PWM check masking time

SR = 00 Guaranteed by scan

13*64/fOSC

–

14*64/fOSC

–

LOAD_SOLx

t_PWM_check

PWM check masking time

SR = 01 Guaranteed by scan

9*64/fOSC

–

10*64/fOSC

–

LOAD_SOLx

t_PWM_check

PWM check masking time

SR = 10/11 Guaranteed by

scan

5*64/fOSC

–

6*64/fOSC

–

LOAD_SOLx

PWM_check_deglitch PWM check fault deglitch time

Guaranteed by scan

0.2

–

µs

LOAD_SOLx

I_safe_pd

Safety switch off pull down

current capability

Design info not tested

–

FS_Gx

Vgs_off_safed

Residual voltage at FS_G pins

with safe off path active

Design info not tested in

production

–

FS_Gx

8.5

Core over temperature

The device internal temperature is monitored against overheating. If an over temperature event is detected, all

solenoid driver outputs are disabled, their enable bit is cleared and their configuration registers are reset, a fault

bit cleared on read is set in the SPI registers (Core Over Temperature D[0] bit in SERVFLT1 register). Once the

over temperature condition is removed the fault information must be cleared to restart the outputs. Core over

temperature is provided with a hysteresis in order to avoid power-on/power-off oscillations when temperature is

around over temperature threshold.

8.5.1

Core over temperature electrical characteristics

5.5 V ≤ VBATP ≤ 19 V; 5.5 V ≤ VSx ≤ 19 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise noticed. All voltages refer to

GNDA pin.

L9305

Safety features

DS12774 - Rev 10

page 45/107

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