L9305 datasheet(50/107 Pages) STMICROELECTRONICS

50 / 107 page

Table 35. SPI time out values

Dec

Bin

SPI Time Out

63 x 8 x 2N [µs]

000

504

001

1008

010

2016

011

4032

100

8064

101

16128

110

32256

111

64512

Reset latch function can reset the device to IDLE state if a certain number of timeout events occur. Enable of this

function (TIMEOUTSPICFG register, D[1:0] ) and the number of timeout events (TIMEOUTSPICFG register,

D[6:5]) is programmed through SPI.

Table 36. Reset latch enable state

En_Res_Latch[1]

(Reset Latch enable)

Dis_Res_Latch[0]

(Reset latch disable)

Reset Latch

Disabled

Enabled

Disabled

Table 37. Time out reset latch counter values

Dec

Bin

Time Out Reset Latch Counter [2N+1]

9.5

SPI channel exception field

MISO frame has 2 bits (IERR) reserved for solenoid channel exceptions. MISO[29] is the OR of all the exceptions

related to Channel 0 and Channel 1, while MISO[30] is the OR of all the exceptions related to Channel 2 and

Channel 3.

MISO[29] = (Ch0.Exception1&0xF87F) | (Ch1.Exception1&0xF87F) | Ch0.Exception2 | Ch1.Exception2

MISO[30] = (Ch2.Exception1&0xF87F) | (Ch3.Exception1&0xF87F) | Ch2.Exception2 | Ch3.Exception2

In this way, it is always possible to detect a failure happening on solenoid channel during every SPI

communication. Details and clearing of the channel exception can be retrieved by reading the dedicated SPI

registers.

L9305

SPI

DS12774 - Rev 10

page 50/107

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