STA333W datasheet(31/50 Pages) STMICROELECTRONICS

tên linh kiện	STA333W

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STA333W

LRCK double trigger protection

Actively prevents double trigger of LRCLK.

Auto EAPD on clock loss

When active will issue a power device power-down signal (EAPD) on clock loss detection.

IC power down

The PWDN register is used to put the IC in a low-power state. When PWDN is 0, the output

begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down

the power stage, then the master clock to all internal hardware except the I²C block is gated.

This puts the IC in a very low power consumption state.

External amplifier power down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed in a low-power state (disabled).

Table 35. LRCK double trigger protection

Bit

R/W

RST

Name

Description

R/W

LDTE

LRCLK double trigger protection enable

Table 36. Auto EAPD on clock loss

Bit

R/W

RST

Name

Description

R/W

ECLE

Auto EAPD on clock loss

Table 37. Power down

Bit

R/W

RST

Name

Description

6R/W

1PWDN

0: power down, low-power condition

1: normal operation

Table 38. External amplifier power down

Bit

R/W

RST

Name

Description

R/W

EAPD

0: external power stage power down active

1: normal operation

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