TAS3103ADBT datasheet(129/154 Pages) TI2

129 / 154 page

4−8

4.4.6

Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus Devices, (1)

PARAMETER

STANDARD MODE

FAST MODE

UNITS

PARAMETER

MIN

MAX

MIN

MAX

UNITS

fSCL

SCL clock frequency

100

400

kHz

tHD-STA

Hold time (repeated) START condition. After this period, the

first clock pulse is generated.

0.6

μs

tLOW

LOW period of the SCL clock

4.7

1.3

μs

tHIGH

HIGH period of the SCL clock

0.6

μs

tSU-STA

Setup time for repeated START

4.7

0.6

μs

tSU-DAT

Data setup time

250

100

μs

tHD-DAT

Data hold time (2)(3)

3.45

0.9

μs

Rise time of both SDA and SCL signals

1000

20 + 0.1 Cb (4)

300

Fall time of both SDA and SCL signals

300

20 + 0.1 Cb (4)

300

tSU-STO

Setup time for STOP condition

0.6

μs

tBUF

Bus free time between a STOP and START condition

4.7

1.3

μs

Capacitive load for each bus line

400

VnL

Noise margin at the LOW level for each connected device

(including hysteresis)

0.1 VDD

VnH

Noise margin at the HIGH level for each connected device

(including hysteresis)

0.2 VDD

NOTES:

1. All values referred to VIHmin and VILmax levels (see Section 4.4.5).

NOTES:

2. Note that SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be valid by the rising and falling

edges of SCL. TI recommends that a minimum 2-k

Ω pullup resistor be used to avoid potential timing issues.

NOTES:

3. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU-DAT ≥ 250 ns must then be

met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU-DAT = 1000 + 250 = 1250 ns (according

to the standard-mode I2C-bus specification) before the SCL line is released.

NOTES:

4. Cb = total capacitance of one bus line in pF.

SDA

SCL

tSU-DAT

tHD-STA

tBUF

tSU-STO

tSP

tSU-STA

tHIGH

tHD-DAT

tLOW

tHD-STA

Figure 4−5. I2C Start and Stop Conditions Timing Waveforms

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