TAS3103ADBT datasheet(56/154 Pages) TI2

56 / 154 page

2−23

simply does not receive all the data. If the master device issues more data-received acknowledges than required to

receive the data for a given subaddress, the master device simply receives complete or partial sets of data, depending

on how many data-received acknowledges are issued from the subaddress(es) that follow.

I2C read transactions, both sequential and random, can impose wait states. For the standard I2C mode

(SCL = 100 kHz), typical wait state time for an 8-MHz microprocessor clock is on the order of 1

μs. For the fast I2C

mode (SCL = 400 kHz) and the same 8-MHz microprocessor clock, typical wait state times are extended up to 4

μs

in duration. Increasing the microprocessor clock frequency lowers the wait state times and for the standard I2C mode,

a higher microprocessor clock can totally eliminate the presence of wait states. For example, increasing the

microprocessor clock to 33 MHz results in no wait states for the standard (100-kHz) I2C mode. For the fast I2C mode,

higher microprocessor clocks shorten the wait state times encountered, but do not totally eliminate their presence.

2.4

Digital Audio Processor (DAP) Arithmetic Unit

The DAP arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient

memory blocks. Figure 2−18 is a block diagram of the arithmetic unit.

76-Bit Adder

Regs

Arithmetic

Engine

Dual-Port

Data RAM

Coefficient

RAM

× 16

Delay Line

RAM

Program

ROM

DAP

Instruction Decoder/Sequencer

Digital Audio Processor

(DAP)

Arithmetic Unit

Figure 2−18. DAP Arithmetic Unit Block Diagram

The DAP arithmetic unit is used to implement all firmware functions—soft volume, loudness compensation, bass and

treble processing, dynamic range control, channel filtering, 3D effects, input and output mixing, spectrum analyzer,

VU meter, and dither.

Figure 2−19 shows the data word structure of the DAP arithmetic unit. Eight bits of overhead or guard bits are provided

at the upper end of the 48-bit DAP word and 8 bits of computational precision or noise bits are provided at the lower

end of the 48-bit word. The incoming digital audio words are all positioned with the most-significant bit abutting the

8-bit overhead/guard boundary. The sign bit in bit 39 indicates that all incoming audio samples are treated as signed

data samples.

CAUTION: Audio data into the TAS3103A is always treated as sign-extended 2s-complement data.

TAS3103ADBT bảng dữ liệu(PDF) 56 Page - Texas Instruments

TAS3103ADBT bảng dữ liệu(HTML) 56 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL