SCANSTA101

SNLS057J – MAY 2002 – REVISED APRIL 2013

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Table 23. TDI_SM LFSR Exponent Register (EXPR) ($07)

Bit(s)

Type

Field

Address Offset

Reset Value

Reset Source

15:3

RO

Reserved

0

0000h

2:0

RW

LFSR

0

000b

SYS_RST

LFSR Exponent<2:0>

LFSR exponent. Binary encoding for the selection between three polynomials.

'000'

No polynomial selected

'001'

Polynomial 1: X32 + X7 + X5 + X3 + X2 + X + 1

'010'

Polynomial 2: X32 + X28 + X27 + X + 1

'011'

Polynomial 3: X32 + X7 + X6 + X2 + 1

Table 24. TDI_SM LFSR LSB Seed Register (LSSEDR) ($08) (1)(2)

Bit(s)

Type

Field

Address Offset

Reset Value

Reset Source

15:0

RW

LSW LFSR Seed

0

0000h

SYS_RST

(1)

LSW LFSR Seed<15:0> is the LS word of the LFSR seed.

(2)

This register along with register MSSEDR form a register pair and should be read/written with two consecutive read/write accesses.

Table 25. TDI_SM LFSR MSB Seed Register (MSSEDR) ($09) (1)(2)

Bit(s)

Type

Field

Address Offset

Reset Value

Reset Source

15:0

RW

MSW LFSR Seed

0

0000h

SYS_RST

(1)

MSW LFSR Seed <15:0> is the MS word of the LFSR seed.

(2)

This register along with register LSSEDR form a register pair and should be read/ written with two consecutive read/write accesses.

Table 26. TDI_SM LFSR LSB Result Register (LSRESR) ($0A) (1)(2)

Bit(s)

Type

Field

Address Offset

Reset Value

Reset Source

15:0

RW

LSW LFSR Result

0

0000h

SYS_RST

(1)

LSW LFSR Result<15:0> is the LS word of the LFSR result.

(2)

This register along with register MSRESR form a register pair and should be read/written with two consecutive read/write accesses.

Table 27. TDI_SM LFSR MSB Result Register (MSRESR) ($0B) (1)(2)

Bit(s)

Type

Field

Address Offset

Reset Value

Reset Source

15:0

RW

MSW LFSR Result

0

0000h

SYS_RST

(1)

MSW LFSR Result<15:0> is the MS word of the LFSR result.

(2)

This register along with register LSRESR form a register pair and should be read/ written with two consecutive read/write accesses.

Table 28. Index Register (INDEXR) ($0C) (1)(2)(3)

Bit(s)

Type

Field

Address Offset

Reset Value

Reset Source

15:0

RW

Index

0

0000h

SYS_RST

(1)

Index<15:0> sets the individual address memory pointer.

(2)

Address memory pointer must be on a long word boundary.

(3)

Writing to this register sets the TDO_SM, TDI_SM, Expected and Mask pointers. These pointers will automatically increment with each

long word read from the TDI_SM space and each long word write to the other TDO_SM, Expected and Mask spaces.

Table 29. Vector Index Register (VINDEXR) ($11) (1)(2)

Bit(s)

Type

Field

Address Offset

Reset Value

Reset Source

15:0

RW

Vector Index

0

0000h

SYS_RST

(1)

Vector Index<15:0> sets the Vector address memory pointer.

(2)

Address memory pointer must be on a long word boundary.

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