SCANSTA101

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SNLS057J – MAY 2002 – REVISED APRIL 2013

CONNECTION DIAGRAM

Figure 2. NFBGA Package Pinout

(Top View)

PIN DESCRIPTIONS

Pin

No. Pins

I/O

Description

Name

VCC

4

N/A

Power

GND

4

N/A

Ground

D(15:0)

16

I/O

Bidirectional Data Bus. Signals are bonded out for the packaged

device.

D(31:16) (1)

16

I/O

Bidirectional Data Bus. These signals are not available in the packaged

device.

A(4:0)

5

I

Address Bus

SCK

1

I

The system clock that drives all internal timing. TCK_SM is a gated,

divided and buffered version of SCK.

INT

1

O

Interrupt Output

OE

1

I

Output enable that will TRI-STATE all 1149.1 "_SM" outputs when high.

DTACK

1

O

DTACK is used to synchronize asynchronous transfers between the

host and the SCANSTA101. When CE is high, DTACK is tristated.

When CE is low, DTACK is enabled. DTACK goes low when data has

been registered and then goes tri-state when the cycle has completed.

R/W

1

I

R/W defines a PPI cycle. Read when high, write when low.

STB

1

I

Strobe is used for timing all PPI transfers. D(15:0), or D(31:0) in 32-bit

mode (1), are at TRI-STATE when STB is high. Data valid setup is with

respect to the falling edge of STB and data valid hold is with respect to

rising edge of STB.

CE

1

I

Chip Enable, when low, enables the PPI for data transfers. CE can

remain low during back-to-back accesses. D(15:0), or D(31:0) in 32-bit

mode (1), and DTACK are tristated when CE is high.

RST

1

I

Asynchronous reset, when low, initializes the SCANSTA101.

TDO

1

O

Test Data Out is the serial scan output from the SCANSTA101. TDO is

enabled when OE is low.

(1)

D(31:16) in the Parallel Processor Interface and TRST1_SM in the Serial Scan Interface are not bonded out for the packaged device.

These are used in the 32-bit IP Macro Mode only.

Copyright © 2002–2013, Texas Instruments Incorporated

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