LM5056, LM5056A

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SNVS827A – OCTOBER 2012 – REVISED APRIL 2013

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

UNIT

VIN, VIN_K, SENSE, OUT to AGND/DGND

-0.3 to 100

SMBA, SCL, SDAI, SDAO, CL, ADR0, ADR1, ADR2, VDD, VAUX, DIODE to AGND/DGND

-0.3 to 6.0

V

VIN to VIN_K, AGND to DGND

-0.3 to 0.3

VIN_K to SENSE

-3.0 to 3.0

HBM

Human body model ESD rating(2)

2.0

kV

TSTG

Storage temperature

-65 to 150

°C

TJ

Junction temperature

150

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and conditions

see Electrical Characteristics Table.

(2)

The human body model is a 100-pF capacitor discharged through a 1.5-k

Ω resistor into each pin.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

NOM

MAX

UNIT

VIN, VIN_K,SENSE, OUT

10

80

VDD

4.5

5.0

5.5

V

VAUX

0

2.97

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and conditions

see the Electrical Characteristics Table.

THERMAL INFORMATION

LM5056

THERMAL METRIC(1)

PWP

UNITS

28 PINS

θJA

Junction-to-ambient thermal resistance(2)

35.6

θJCtop

Junction-to-case (top) thermal resistance(3)

19.9

θJB

Junction-to-board thermal resistance(4)

16.8

°C/W

ψJT

Junction-to-top characterization parameter(5)

0.5

ψJB

Junction-to-board characterization parameter(6)

16.7

θJCbot

Junction-to-case (bottom) thermal resistance(7)

2.9

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter,

ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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