IP1000A LF
Preliminary Data Sheet
47/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.2
PCI Configuration Space Registers
3.2.2.1
CapId0
Class............................. PCI Configuration Registers, Power Management
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x50
Default Value ................ 0x01
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
7..0
CapId
Capabilities ID. CapId indicates the type of the
capability data structure for the IP1000A LF. CapId
is set to the value 0x01 to indicate a PCI Power
Management structure.
R
3.2.2.2
CapId1
Class............................. PCI Configuration Registers, Power Management
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x60
Default Value ................ 0x07
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
7..0
CapId
Capabilities ID. CapId indicates the type of the
capability data structure for the IP1000A LF.
R
3.2.2.3
CapPtr
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x34
Default Value ................ 0x50
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
7..0
CapPtr
Capabilities
Pointer.
CapPtr
indicates
the
beginning of a chain of registers which describe
enhanced functions. CapPtr register returns 0x50,
which is the address of the first in a series of
power management registers.
R
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