IP1000A LF
Preliminary Data Sheet
34/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
the
IntStatus
register)
will
occur
when
CarrierSenseErrors reaches a value of 0xC000.
CarrierSenseErrors is enabled by writing a logic 1
to the StatisticsEnable bit in the MACCtrl register,
and a logic 0 to the CarrierSenseErrors bit within
the StatisticsMask register.
3.2.1.6
FramesAbortXSColls
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xFC
Default Value ................ 0x0000
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
15..0
FramesAbortXS-
Colls
Frames Aborted Due to Excess Collisions counts
the number of frames which are not transmitted
successfully
due
to
excessive
collisions.
FramesAbortXSColls will wrap around to zero
after reaching 0xFFFF. See IEEE 802.3 Clause
30.3.1.1.11.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
FramesAbortXSColls reaches a value of 0xC000.
FramesAbortXSColls is enabled by writing a logic
1 to the StatisticsEnable bit in the MACCtrl
register, and a logic 0 to the FramesAbortXSColls
bit within the StatisticsMask register.
R/W
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