IP1000A LF
Preliminary Data Sheet
39/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.1.14 InRangeLengthErrors
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xCA
Default Value ................ 0x0000
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
15..0
InRangeLength
Errors
In Range Length Errors is a count of the number
of frames with the Length/Type field value
between the minimum unpadded MAC client data
size and the maximum allowed MAC client data
size, inclusive, that does not match the number of
MAC
client
data
octets
received.
InRangeLengthErrors also increments for frames
whose Length/Type field value is less than the
minimum allowed unpadded MAC client data size,
and the number of MAC client data octets
received is greater than the minimum unpadded
MAC client data size. InRangeLengthErrors will
wrap around to zero after reaching 0xFFFF. See
IEEE 802.3 Clause 30.3.1.1.23.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
InRangeLengthErrors reaches a value of 0xC000.
InRangeLengthErrors is enabled by writing a logic
1 to the StatisticsEnable bit in the MACCtrl
register, and a logic 0 to the InRangeLengthErrors
bit within the StatisticsMask register.
R/W
3.2.1.15 LateCollisions
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xE8
Default Value ................ 0x00000000
Access Rule.................. Double Word
Width ............................ 32 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
31..0
LateCollisions
Late Collisions is a count of the number of times
that a collision has been detected later than 1 slot
time into the transmitted frame. LateCollisions will
wrap around to zero after reaching 0xFFFFFFFF.
See IEEE 802.3 Clause 30.3.1.1.10.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
R/W
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