S29GL01GS10DFIV13 datasheet(77/108 Pages) CYPRESS

77 / 108 page

Document Number: 001-98285 Rev. *R

Page 77 of 108

S29GL01GS/S29GL512S

S29GL256S/S29GL128S

Figure 11.3 Power-Up Diagram

11.3.2

Hardware (Warm) Reset

During Hardware Reset (tRPH) the device will draw ICC5 current.

When RESET# continues to be held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS,

the standby current is greater.

If a Cold Reset has not been completed by the device when RESET# is asserted Low after tVCS, the Cold Reset# EA will be

performed instead of the Warm RESET#, requiring tVCS time to complete.

See Figure 11.4 on page 77.

After the device has completed POR and entered the Standby state, any later transition to the Hardware Reset state will initiate the

Warm Reset Embedded Algorithm. A Warm Reset is much shorter than a Cold Reset, taking tens of µs (tRPH) to complete. During

the Warm Reset EA, any in progress Embedded Algorithm is stopped and the EAC is returned to its POR state without reloading

EAC algorithms from non-volatile memory. After the Warm Reset EA completes, the interface will remain in the Hardware Reset

state if RESET# remains Low. When RESET# returns High the interface will transit to the Standby state. If RESET# is High at the

end of the Warm Reset EA, the interface will directly transit to the Standby state.

If POR has not been properly completed by the end of tVCS, a later transition to the Hardware Reset state will cause a transition to

the Power-on Reset interface state and initiate the Cold Reset Embedded Algorithm. This ensures the device can complete a Cold

Reset even if some aspect of the system Power-On voltage ramp-up causes the POR to not initiate or complete correctly. The RY/

BY# pin is Low during cold or warm reset as an indication that the device is busy performing reset operations.

Hardware Reset is initiated by the RESET# signal going to VIL.

Figure 11.4 Hardware Reset

VCC

VIO

RESET#

CE#

tRH

tVIOS

tVCS

tCEH

RESET#

CE#

tRP

tRPH

tRH

tCEH

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