S29GL01GS10DFIV13 datasheet(65/108 Pages) CYPRESS

65 / 108 page

Document Number: 001-98285 Rev. *R

Page 65 of 108

S29GL01GS/S29GL512S

S29GL256S/S29GL128S

8.3

Versatile I/O Feature

The maximum output voltage level driven by, and input levels acceptable to, the device are determined by the VIO power supply.

This supply allows the device to drive and receive signals to and from other devices on the same bus having interface signal levels

different from the device core voltage.

8.4

Ready/Busy# (RY/BY#)

RY/BY# is a dedicated, open drain output pin that indicates whether an Embedded Algorithm, Power-On Reset (POR), or Hardware

Reset is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in a command sequence,

when VCC is above VCC minimum during POR, or after the falling edge of RESET#. Since RY/BY# is an open drain output, several

RY/BY# pins can be tied together in parallel with a pull up resistor to VIO.

If the output is Low (Busy), the device is actively erasing, programming, or resetting. (This includes programming in the Erase

Suspend mode). If the output is High (Ready), the device is ready to read data (including during the Erase Suspend mode), or is in

the standby mode.

Table 5.3, Data Polling Status on page 39 shows the outputs for RY/BY# in each operation.

If an Embedded algorithm has failed (Program / Erase failure as result of max pulses or Sector is locked),

RY/BY# will stay Low (busy) until status register bits 4 and 5 are cleared and the reset command is issued. This includes Erase or

Programming on a locked sector.

8.5

Hardware Reset

The RESET# input provides a hardware method of resetting the device to standby state. When RESET# is driven Low for at least a

period of tRP, the device immediately:



terminates any operation in progress,



exits any ASO,



tristates all outputs,



resets the Status Register,



resets the EAC to standby state.



CE# is ignored for the duration of the reset operation (tRPH).



To meet the Reset current specification (ICC5) CE# must be held High.

To ensure data integrity any operation that was interrupted should be reinitiated once the device is ready to accept another

command sequence.

S29GL01GS10DFIV13 bảng dữ liệu(PDF) 65 Page - Cypress Semiconductor

S29GL01GS10DFIV13 bảng dữ liệu(HTML) 65 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL