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AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

2.

Overview

2.1

Introduction

The AT42QT1060 (QT1060) is a digital burst mode charge-transfer (QT™) capacitive sensor driver designed

specifically for mobile phone applications. The device can sense from two to six keys; up to four keys can be

disabled by not installing their respective sense capacitors (Cs). It also has up to seven configurable input/output

lines, with Pulse Width Modulation (PWM) for driving LEDs.

This device includes all signal processing functions necessary to provide stable sensing under a wide variety of

changing conditions, and the outputs are fully de-bounced. Only a few external parts are required for operation.

The QT1060 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the effects of external

noise, and to suppress RF emissions.

2.2

Keys

The QT1060 can have a minimum of two keys and a maximum of six keys. These can be constructed in different

shapes and sizes. See “Features” on page 1 for the recommended dimensions.

Unused keys should be disabled by removing the corresponding Cs and Rs components and connecting the SNS

pins as shown in the If Unused column of Table on page 2. The unused keys are always pared from the burst

sequence in order to optimize speed. See Section 6. on page 25 about setting up the keys.

2.3

Standalone Mode

The QT1060 can operate in a standalone mode where an I

2C-compatible interface is not required. To enter

standalone mode, connect SDA to Vss and SCL to Vdd before powering up the QT1060.

In standalone mode the default start-up values are used except for the I/O mask (Address 23). The I/O mask is

configured so that all the I/Os are outputs (I/O mask =

0x7F). This means that key detection is reported via the

respective I/Os.

2.4

I/O Lines

2.4.1

Overview

There is an input/output (I/O) port consisting of seven lines that can be individually programmed as inputs or outputs.

They can be either a digital type or PWM. The PWM level can be set to 256 possible values and is common to all

lines.

The I/O lines are normally initialized as inputs. However, if an I2C interface is not used and the SDA and SCL pins

are connected to Vss and Vdd respectively, then the I/O lines are initialized as outputs (see Section 2.3).

The outputs can also be linked to either the detection channels or the output register to allow the outputs to be either

user controlled or to indicate detection. These options can be set in the pin control masks (see Table on page 16).

Unused I/O lines should be disabled by connecting as shown in the If Unused column of Table 1-1 on page 2. See

Section 6. on page 25 about setting up the I/O lines.

2.4.2

I/O Mask

A 1 in any bit position of this mask sets the corresponding pin to an output. If a bit is 0, the pin is an input and the

function of the PWM, detect and active state masks will not matter for this pin. The level of the input pins is reflected

in the input Status register. Changes to the logic levels on the inputs cause the CHG line to be asserted.