ADIN6310BBCZ datasheet(82/86 Pages) AD

82 / 86 page

Data Sheet

ADIN3310/ADIN6310

LAYOUT GUIDELINES

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Rev. A | 82 of 86

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Avoid crossover of the signals where possible. Avoid stubs on all

signal traces.

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Route traces over a continuous reference plane with no interrup-

tions to reduce inductance.

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It is recommended to route traces on the same layer.

The switch provides user programmability to adjust the drive current

of the RGMII pins to help improve signal integrity and minimize

ringing. Alternatively, series termination resistors can be placed

on all RGMII pins if further tuning is required. When event series

termination resistors are used, place these resistors close to the

output pins on each side.

SGMII

The SGMII is a serial interface using two differential pairs to transfer

information between the switch and SFP or host, using less pins

and requiring less routing and traces compared to the RMII and

RGMII. The SGMII transmits at 1.25 Gbps and requires external AC

coupling with 0.1 μF capacitors (typically included in the SFP mod-

ules). The SGMII is available on Port 1 to Port 4 of the ADIN6310

and Port 1 to Port 2 of the ADIN3310. The interface is capable of

10 Mbps, 100 Mbps, and 1 Gbps full duplex communication with

autonegotiation or forced modes. The SGMII pins can be connected

to an SFP transceiver for fiber communication or over a backplane.

The SGMII lines are differential and must be length matched to

connector to within 50 mils. Also ensure the following:

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Route the Px_STxP and Px_STxN and Px_SRxP and Px_SRxN

signal traces as 100 Ω differential line route signals in homoge-

nous internal layers using buried and blind vias. Keep impedan-

ces constant throughout because any discontinuities can affect

signal integrity.

►

Co-planar routing is recommended—stitch vias on the ground

shield on both sides of the traces or use a ground pour.

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Keep routing lengths short and avoid stubs.

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Each pair must be routed in parallel and on the same layer, with

trace widths kept the same throughout and length matched to

within 50 mil.

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Avoid any right angles on these traces (use curves in traces or

45° angles).

►

Avoid crossing of differential traces with other lines and among

each other. Place the components such that crossing of differen-

tial pairs is not necessary.

►

Route differential pairs without vias if possible. In the case of

signal transition from layer to layer, provide a symmetrical GND

via adjacent to the signal via.

►

Components or vias on the differential pair must be symmetrical.

►

Where possible, ensure that a solid return paths are underneath

all signal traces. Avoid routing signal traces across plane splits.

Figure 64. Things to Avoid when Routing Differential Pairs

MDIO

The switch has a controller MDC or MDIO interface that is a 2-wire

bus used to manage the control and status of the external Ethernet

PHYs connected to the switch MAC interfaces. The MDIO signal

line must have a 1.5 kΩ pull-up resistor to the VDDIO_x line.

Length match the MDIO interface traces to within 100 mils.

SPI

The switch contains a synchronous SPI-compatible interface that

can be optionally used as the host interface. The SPI port supports

32-bit data transfers, is a target interface, and can be configured as

a standard SPI, dual SPI, or quad SPI. Length match SPI traces to

within 100 mils.

Power and Ground Plane

For the best high-frequency decoupling, ensure that the power and

return planes are not more than 3 mils to 4 mils apart. Closer is the

better for low inductance connections and interplane capacitance.

Also, ensure that the following is done:

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Avoid overlapping power planes.

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Avoid routing power planes on the edge of the board.

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Avoid routing power planes like traces, and use planes.

Isolation Guidelines—RJ45 Layout

For better electomagnetic interference (EMI) performance consider

using an inbuilt common-mode choke (CMC), 12-core magnetic

RJ45 connector connected to the Ethernet PHY and provide a

high decoupling connection between the digital GND return and the

chassis GND.

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