ADIN6310BBCZ datasheet(26/86 Pages) AD

26 / 86 page

Data Sheet

ADIN3310/ADIN6310

PIN CONFIGURATION AND PIN DESCRIPTIONS

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Rev. A | 26 of 86

Table 14. Pin Function Descriptions (Continued)

ADIN6310 Ball No.

Mnemonic

Type1

Internal

Termination at

Reset2

Power

Domain2

Description

J14

TIMER1

I/O

Pull-up

VDDIO_A

Timer or GPIO. The boot strapping pin is used to define the host interface

origin and operation.

H16

TIMER2

I/O

Pull-down

VDDIO_A

Timer or GPIO. The boot strapping pin is used to define the host interface

origin and operation.

H15

TIMER3

I/O

Pull-down

VDDIO_A

Timer or GPIO. The boot strapping pin is used to define the host interface

origin and operation.

K16

GPIO0

I/O

Pull-down

VDDIO_A

GPIO.

K14

GPIO1

I/O

Pull-down

VDDIO_A

GPIO.

K15

GPIO2

I/O

Pull-down

VDDIO_A

GPIO and Activity on Industrial Ethernet Engine Port 1.

J16

GPIO3

I/O

Pull-down

VDDIO_A

GPIO and Activity on Industrial Ethernet Engine Port 2.

Management Interface

D15

MDC

High-Z

VDDIO_B

Management Data Clock Output up to 5.5 MHz.

D14

MDIO

I/O

High-Z

VDDIO_B

Management Data Bidirectional Line Synchronous to the MDC Clock. The

MDIO pin requires a 1.5 kΩ pull-up resistor to VDDIO_B.

Serial Interface

This interface supports standard SPI, dual SPI and quad SPI

communication.

L14

SPI_SS

Pull-up

VDDIO_A

Chip Select Input, Active Low. The boot strapping pin is used to define the

host interface origin and operation.

L16

SPI_SCLK

I/O

Pull-down

VDDIO_A

Clock Input.

L15

SPI_SIO0

I/O

Pull-down

VDDIO_A

Serial Input and Output 0 for the Quad SPI. The boot strapping pin is used

to define the host interface origin and operation. This pin is the Serial Input

and Output 0 for the dual SPI, and the serial data input (SDI) for the SPI.

M16

SPI_SIO1

I/O

Pull-down

VDDIO_A

Serial Input and Output 1 for the Quad SPI. The boot strapping pin is used

to define the host interface origin and operation. This pin is the Serial Input

and Output 1 for the dual SPI, and the serial data output (SDO) for the SPI.

M15

SPI_SIO2

I/O

Pull-down

VDDIO_A

Serial Input and Output 2 for the Quad SPI. The boot strapping pin is used

to define the host interface origin and operation.

M14

SPI_SIO3

I/O

Pull-down

VDDIO_A

Serial Input and Output 3 for the Quad SPI.

Port 0 Interface

P10

P0_RSTN

Pull-down

VDDIO_A

Port 0 PHY Reset. Active low output.

T15

P0_TXC

Pull-down

VDDIO_A

Port 0 Transmit Clock. In RGMII mode, P0_TXC provides the clock output

of 125 MHz for 1 Gbps speed, of 25 MHz for 100 Mbps, and of 2.5 MHz for

10 Mbps. In RMII mode, the 50 MHz REF_CLK is the input or output and

configured through strapping or software.

R14

P0_TXD0

Pull-down

VDDIO_A

Port 0 RGMII and RMII Transmit Data 0 Output.

T14

P0_TXD1

Pull-down

VDDIO_A

Port 0 RGMII and RMII Transmit Data 1 Output.

R13

P0_TXD2

Pull-down

VDDIO_A

Port 0 RGMII Transmit Data 2 Output.

T13

P0_TXD3

Pull-down

VDDIO_A

Port 0 RGMII Transmit Data 3 Output.

P14

P0_TXCTL

Pull-down

VDDIO_A

Port 0 RGMII Transmit Control Signal. In RGMII mode, this pin is a

combination of the TX_EN and TX_ER signals using both edges of TXC.

In RMII mode, this is the transmit enable input from the MAC to the PHY

(TX_EN), which indicates that transmission data is available on the data

lines.

R16

P0_RXC

Pull-down

VDDIO_A

Port 0 Receive Clock Input. In RGMII mode, expect the clock input of 125

MHz for 1 Gbps, of 25 MHz for 100 Mbps, and of 2.5 MHz for 10 Mbps.

P15

P0_RXD0

Pull-down

VDDIO_A

Port 0 RGMII and RMII Receive Data 0 Input.

P16

P0_RXD1

Pull-down

VDDIO_A

Port 0 RGMII and RMII Receive Data 1 Input.

N15

P0_RXD2

Pull-down

VDDIO_A

Port 0 RGMII Receive Data 2 Input.

N16

P0_RXD3

Pull-down

VDDIO_A

Port 0 RGMII Receive Data 3 Input. In RMII mode, this pin is RX_ER. When

asserted high, it indicates that the PHY has detected a receive error.

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