ADIN6310BBCZ datasheet(51/86 Pages) AD

51 / 86 page

Data Sheet

ADIN3310/ADIN6310

HOST INTERFACE

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Rev. A | 51 of 86

The switch requires management from an external host and stack

processor. The connection of the host to the switch is flexible

and configured using hardware strapping pins that are sampled

when the switch is brought out of reset. The switch then knows

where the host resides and how to communicate with it. Run-time

configuration to change the host interface is not supported.

The host communication port can be connected over the SPI

port or an Ethernet MAC interface (SGMII, RMII, or RGMII). The

hardware strapping pins used to select the host interface are the

four TIMERx pins, three of the SPI_SIOx pins, and the SPI_SS pin.

The hardware strapping pins have internal pull-up and pull-downs

to provide a default host interface of standard SPI. Alternatively,

the user can override the default by adding external strapping

resistors to select a different SPI or an Ethernet host interface.

When the host interface is a MAC host, the interface can be any

one of the switch ports, with the levels sensed on the SPI_SIOx

pins determining which port is to be used. Port 0 is recommended

as the host interface if the host is running a different input and

output voltage rail to the supply used for the external physical layer

devices connected to the other Ethernet ports, because the VDDIO

supply rails can be partitioned, with Port 0 from the VDDIO_A rail

and all other ports from the VDDIO_B rail.

There are a number of possible host interface options available as

detailed in Table 22.

HOST INTERFACE STRAPPING PINS

There are eight inputs and outputs used for configuration strapping

listed in Table 22. The level of the strapping pins is sampled on the

rising edge of RESET_N after power on. The hardware strapping

is used to let the packet assist engine know the interface location

of the host and defines the primary host communication protocol as

SPI or Ethernet.

Table 22. Boot Strapping Pin Configuration—Host Interface (SPI or Ethernet)

Function

SIO21, 2 SIO12

SIO02

SPI_SS

TIMER3

TIMER2

TIMER1

TIMER03

Notes

Default Internal

Pull-

down

Pull-

down

Pull-

down

Pull-up

Pull-down

Pull-up

RGMII 100 Mbps

No Clock Delays4

ds5

Receive Clock Delay

Transmit Clock Delay

Receive and Transmit

Clock Delays

RGMII 1 Gbps

No Clock Delays

Receive Clock Delay

Transmit Clock Delay

Receive and Transmit

Clock Delays

RMII 10 Mbps

RMII CLK (Internal)

Switch internal clock provided out to the

PHY or host

RMII CLK (External)

External clock source provided to the

PHY or host and switch

RMII 100 Mbps

RMII CLK (Internal)

Switch internal clock provided out to the

PHY or host

RMII CLK (External)

External clock source provided to the

PHY or host and switch

SGMII

100BASE-FX

SGMII 1000 Mbps

SGMII 100 Mbps

1000BASE-KX

SPI Enabled

Single (Default)

Default setting

Dual

Quad

Low drive strength

Quad

High drive strength

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