MPC8280 datasheet(392/1386 Pages) FREESCALE

392 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-84

Freescale Semiconductor

9.12.3.4.7

Messaging Unit Control Register (MUCR)

This register allows software to enable and setup the size of the inbound and outbound FIFOs. MUCR

should be accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from

the PCI bus have undefined results.

Figure 9-79. Messaging Unit Control Register (MUCR)

—

Reserved, should be cleared.

IPQIM

Inbound post queue interrupt mask

0 Inbound post queue interrupt is allowed.

1 Inbound post queue interrupt is masked.

MCIM

Machine check interrupt mask

0 Machine check interrupt from the inbound doorbell register is allowed.

1 Machine check interrupt is masked.

IDIM

Inbound doorbell interrupt mask

0 Inbound doorbell interrupt is allowed.

1 Inbound doorbell interrupt is masked.

—

Reserved, should be cleared.

IM1IM

Inbound message 1 interrupt mask

0 Inbound doorbell interrupt is allowed.

1 Inbound doorbell interrupt is masked.

IM0IM

Inbound message 0 interrupt mask

0 Inbound message 0 interrupt is allowed.

1 Inbound message 0 interrupt is masked.

Field

—

Reset

0000_0000_0000_0002

R/W

Addr

0x104E6

Field

—

CQS

CQE

Reset

0000_0000_0000_0000

R/W

Addr

0x104E4

Table 9-63. IMIMR Field Descriptions (continued)

Bits

Name

Description

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