MPC8280 datasheet(17/1386 Pages) FREESCALE

17 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

xvii

Contents

Paragraph

Number

Title

Page

Number

9.12.3.4.7

Messaging Unit Control Register (MUCR) ...................................................... 9-84

9.12.3.4.8

Queue Base Address Register (QBAR) ............................................................ 9-85

9.13

DMA Controller............................................................................................................. 9-86

9.13.1

DMA Operation ......................................................................................................... 9-86

9.13.1.1

DMA Direct Mode................................................................................................. 9-87

9.13.1.2

DMA Chaining Mode ............................................................................................ 9-87

9.13.1.3

DMA Coherency.................................................................................................... 9-88

9.13.1.4

Halt and Error Conditions...................................................................................... 9-88

9.13.1.5

DMA Transfer Types ............................................................................................. 9-88

9.13.1.6

DMA Registers ...................................................................................................... 9-89

9.13.1.6.1

DMA Mode Registers 0–3 (DMAMRx) .......................................................... 9-89

9.13.1.6.2

DMA Status Registers 0–3 (DMASRx) ............................................................ 9-91

9.13.1.6.3

DMA Current Descriptor Address Registers 0–3 (DMACDARx) ................... 9-92

9.13.1.6.4

DMA Source Address Registers 0–3 (DMASARx) ......................................... 9-93

9.13.1.6.5

DMA Destination Address Registers 0–3 (DMADARx) ................................. 9-94

9.13.1.6.6

DMA Byte Count Registers 0–3 (DMABCRx) ................................................ 9-94

9.13.1.6.7

DMA Next Descriptor Address Registers 0–3 (DMANDARx) ....................... 9-95

9.13.2

DMA Segment Descriptors........................................................................................ 9-96

9.13.2.1

Descriptor in Big-Endian Mode............................................................................. 9-97

9.13.2.2

Descriptor in Little-Endian Mode.......................................................................... 9-98

9.14

Error Handling ............................................................................................................... 9-98

9.14.1

Interrupt and Error Signals ........................................................................................ 9-99

9.14.1.1

PCI Bus Error Signals............................................................................................ 9-99

9.14.1.1.1

System Error (SERR) ........................................................................................ 9-99

9.14.1.1.2

Parity Error (PERR)........................................................................................... 9-99

9.14.1.1.3

Error Reporting.................................................................................................. 9-99

9.14.1.2

Illegal Register Access Error ................................................................................. 9-99

9.14.1.3

PCI Interface ........................................................................................................ 9-100

9.14.1.3.1

Address Parity Error ........................................................................................ 9-100

9.14.1.3.2

Data Parity Error.............................................................................................. 9-100

9.14.1.3.3

Master-Abort Transaction Termination ........................................................... 9-100

9.14.1.3.4

Target-Abort Error ........................................................................................... 9-101

9.14.1.3.5

NMI ................................................................................................................. 9-101

9.14.1.4

Embedded Utilities .............................................................................................. 9-101

9.14.1.4.1

Outbound Free Queue Overflow ..................................................................... 9-101

9.14.1.4.2

Inbound Post Queue Overflow ........................................................................ 9-101

9.14.1.4.3

Inbound DoorBell Machine Check.................................................................. 9-101

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