MPC8280 datasheet(33/1386 Pages) FREESCALE

33 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

xxxiii

Contents

Paragraph

Number

Title

Page

Number

29.8.1.2.1

TDM Clock...................................................................................................... 29-39

29.8.1.2.2

Synchronization Pulse ..................................................................................... 29-39

29.8.1.2.3

SIRAM Programming...................................................................................... 29-39

29.8.1.2.4

MCC Initialization ........................................................................................... 29-40

29.8.1.2.5

CPM Bandwidth .............................................................................................. 29-40

29.8.1.2.6

CPM Priority.................................................................................................... 29-40

29.8.1.2.7

Bus Latency ..................................................................................................... 29-41

29.8.1.3

Recovery from GUN Errors................................................................................. 29-41

29.8.1.4

Global Overrun (GOV)........................................................................................ 29-41

29.9

MCC Buffer Descriptors.............................................................................................. 29-41

29.9.1

Receive Buffer Descriptor (RxBD) ......................................................................... 29-42

29.9.2

Transmit Buffer Descriptor (TxBD) ........................................................................ 29-44

29.10

MCC Initialization and Start/Stop Sequence ............................................................... 29-46

29.10.1

Stopping and Restarting a Single-Channel .............................................................. 29-47

29.10.2

Stopping and Restarting a Superchannel ................................................................. 29-47

29.11

MCC Latency and Performance .................................................................................. 29-48

Chapter 30

Fast Communications Controllers (FCCs)

30.1

Overview........................................................................................................................ 30-1

30.2

General FCC Mode Registers (GFMRx) ....................................................................... 30-3

30.2.1

General FCC Expansion Mode Register (GFEMR) .................................................. 30-7

30.3

FCC Protocol-Specific Mode Registers (FPSMRx) ...................................................... 30-8

30.4

FCC Data Synchronization Registers (FDSRx)............................................................. 30-8

30.5

FCC Transmit-on-Demand Registers (FTODRx).......................................................... 30-9

30.6

FCC Buffer Descriptors ............................................................................................... 30-10

30.7

FCC Parameter RAM................................................................................................... 30-12

30.7.1

FCC Function Code Registers (FCRx) .................................................................... 30-14

30.8

Interrupts from the FCCs ............................................................................................. 30-14

30.8.1

FCC Event Registers (FCCEx) ................................................................................ 30-15

30.8.2

FCC Mask Registers (FCCMx) ............................................................................... 30-15

30.8.3

FCC Status Registers (FCCSx)................................................................................ 30-15

30.9

FCC Initialization ........................................................................................................ 30-15

30.10

FCC Interrupt Handling ............................................................................................... 30-16

30.10.1

FCC Transmit Errors................................................................................................ 30-16

30.10.1.1

Re-Initialization Procedure .................................................................................. 30-17

30.10.1.2

Recovery Sequence.............................................................................................. 30-17

30.10.1.3

Adjusting Transmitter BD Handling.................................................................... 30-17

30.11

FCC Timing Control .................................................................................................... 30-17

30.12

Disabling the FCCs On-the-Fly ................................................................................... 30-20

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