MPC8280 datasheet(391/1386 Pages) FREESCALE

391 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-83

9.12.3.4.6

Inbound Message Interrupt Mask Register (IMIMR)

This register contains the interrupt mask of the I2O, door bell, and message register events generated by

the PCI master. IMIMR should be accessed only from the 60x bus and only in agent mode. Accesses while

in host mode or from the PCI bus have undefined results.

Figure 9-78. Inbound Message Interrupt Mask Register (IMIMR)

Table 9-63 describes IMIMR fields.

MCI

Machine check interrupt. When set indicates that a machine check interrupt

condition has been generated by setting the Inbound doorbell register’s bit 31.

The interrupt is cleared by resetting the Inbound doorbell register’s bit 31.

IDI

Inbound doorbell interrupt. When set indicates that there is an Inbound

Doorbell interrupt.

—

Reserved, should be cleared.

IM1I

R/Write 1

to clear

Inbound message 1 interrupt. When set indicates that there is an Inbound

message 1 interrupt.

IM0I

R/Write 1

to clear

Inbound message 0 interrupt. When set indicates that there is an Inbound

message 0 interrupt.

Field

—

Reset

0000_0000_0000_0000

R/W

Addr

0x10486

Field

—

OFOIM IPOIM

—

IPQIM MCIM IDIM

—

IM1IM IM0IM

Reset

0000_0000_0000_0000

R/W

Addr

0x10484

Table 9-63. IMIMR Field Descriptions

Bits

Name

Description

31–9

—

Reserved, should be cleared.

OFOIM

Outbound free overflow interrupt mask

0 Outbound free overflow interrupt is allowed.

1 Outbound free overflow interrupt is masked.

IPOIM

Inbound post overflow interrupt mask

0 Inbound post overflow interrupt is allowed.

1 Inbound post overflow interrupt is masked.

Table 9-62. IMISR Field Descriptions (continued)

Bits

Name

Access

Description

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