MPC8280 datasheet(390/1386 Pages) FREESCALE

390 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-82

Freescale Semiconductor

9.12.3.4.5

Inbound Message Interrupt Status Register (IMISR)

This register contains the interrupt status of the I2O, door bell, and message register events. Writing a 1 to

the corresponding set bit will clear the bit. The events are generated by the PCI masters. IMISR should be

accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from the PCI bus

have undefined results.

Figure 9-77. Inbound Message Interrupt Status Register (IMISR)

Table 9-62 describes IMISR fields.

OM1IM

Outbound message 1 interrupt mask

0 Outbound message 1 interrupt is allowed.

1 Outbound message 1 interrupt is masked.

OM0IM

Outbound message 0 interrupt mask

0 Outbound message 0 interrupt is allowed.

1 Outbound message 0 interrupt is masked.

Field

—

Reset

0000_0000_0000_0000

R/W

Refer to Table 9-62.

Addr

0x10482

Field

—

OFOI IPOI

—

IPQI

MCI

IDI

—

IM1I

IM0I

Reset

0000_0000_0000_0000

R/W

Refer to Table 9-62.

Addr

0x10480

Table 9-62. IMISR Field Descriptions

Bits

Name

Access

Description

31–9

—

Reserved, should be cleared.

OFOI

R/Write 1

to clear

Outbound Free Overflow Interrupt. When set indicates that the Outbound

Free_FIFO Head pointer is equal to the Outbound Free_FIFO Tail pointer and

the queue is full. A machine check interrupt is generated.

IPOI

R/Write 1

to clear

Inbound Post Overflow Interrupt. When set indicates that the Inbound

Post_FIFO Head pointer is equal to the Inbound Post_FIFO Tail pointer and the

queue is full. A machine check interrupt is generated.

—

Reserved, should be cleared.

IPQI

R/Write 1

to clear

Inbound Post Queue Interrupt. When set indicates that the PCI master has

posted an MFA to the Inbound Post queue.

Table 9-61. OMIMR Field Descriptions (continued)

Bits

Name

R/W

Description

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