TDA4VM21 datasheet(270/331 Pages) TI

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Table 6-86. MMC1/2 DLL Delay Mapping for All Timing Modes (continued)

MMCSD12_SS_PHY_CTRL_4_REG

MMCSD12_SS_PHY_CTRL_5_REG

BIT FIELD

[20]

[15:12]

[8]

[4:0]

[2:0]

BIT FIELD NAME

OTAPDLYENA OTAPDLYSEL ITAPDLYENA

ITAPDLYSEL

CLKBUFSEL

MODE

DESCRIPTION

DELAY

ENABLE

DELAY

VALUE

INPUT

DELAY

ENABLE

INPUT

DELAY

VALUE

DELAY

BUFFER

DURATION

UHS-I

SDR50

4-bit PHY operating

1.8 V, 100 MHz

0x1

0xC

0x1

Tuning

0x7

UHS-I

DR50

4-bit PHY operating

1.8 V, 50 MHz

0x1

0xC

0x1

0x2

0x7

UHS-I

SDR104

4-bit PHY operating

1.8, V 200 MHz

0x1

0x5

0x1

Tuning

0x7

Table 6-87 presents timing conditions for MMC1.

Table 6-87. MMC1/2 Timing Conditions

PARAMETER

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

Default Speed, High Speed

0.69

2.06

V/ns

UHS–I SDR12, UHS–I SDR25

0.34

1.34

V/ns

OUTPUT CONDITIONS

Output load capacitance

All modes

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

UHS–I DDR50

240

1134

All other modes

126

1386

td(Trace Mismatch

Delay)

Propagation delay mismatch across all

traces

UHS–I DDR50, UHS–I SDR104

All other modes

100

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

270

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