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TDA4VM21 bảng dữ liệu(PDF) 1 Page - Texas Instruments

tên linh kiện TDA4VM21
Giải thích chi tiết về linh kiện  TDA4VM Processors
PDF  331 Pages
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TDA4VM21 bảng dữ liệu(HTML) 1 Page - Texas Instruments

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TDA4VM Processors
1 Features
Processor cores:
• C7x floating point, vector DSP, up to 1.0GHz, 80
GFLOPS, 256 GOPS
• Deep-learning matrix multiply accelerator (MMA),
up to 8 TOPS (8b) at 1.0GHz
• Vision Processing Accelerators (VPAC) with Image
Signal Processor (ISP) and multiple vision assist
accelerators
• Depth and Motion Processing Accelerators
(DMPAC)
• Dual 64-bit Arm® Cortex®-A72 microprocessor
subsystem at up to 2.0GHz
– 1MB shared L2 cache per dual-core Cortex®-
A72 cluster
– 32KB L1 DCache and 48KB L1 ICache per
Cortex®-A72 core
• Six Arm® Cortex®-R5F MCUs at up to 1.0GHz
– 16K I-Cache, 16K D-Cache, 64K L2 TCM
– Two Arm® Cortex®-R5F MCUs in isolated MCU
subsystem
– Four Arm® Cortex®-R5F MCUs in general
compute partition
• Two C66x floating point DSP, up to 1.35GHz,
40GFLOPS, 160GOPS
• 3D GPU PowerVR® Rogue 8XE GE8430, up to
750MHz, 96GFLOPS, 6Gpix/sec
• Custom-designed interconnect fabric supporting
near max processing entitlement
Memory subsystem:
• Up to 8MB of on-chip L3 RAM with ECC and
coherency
– ECC error protection
– Shared coherent cache
– Supports internal DMA engine
• External Memory Interface (EMIF) module with
ECC
– Supports LPDDR4 memory types
– Supports speeds up to 4266MT/s
– 32-bit data bus with inline ECC
• General-Purpose Memory Controller (GPMC)
• 512KB on-chip SRAM in MAIN domain, protected
by ECC
Functional Safety:
• Functional Safety-Compliant targeted (on select
part numbers)
– Developed for functional safety applications
– Documentation will be available to aid ISO
26262/IEC 61508 functional safety system
design up to ASIL-D/SIL-3 targeted
– Systematic capability up to ASIL-D/SC-3
targeted
– Hardware integrity up to ASIL-D/SIL-3 targeted
for MCU Domain
– Hardware integrity up to ASIL-B/SIL-2 targeted
for Main Domain
– Safety-related certifications
• ISO 26262 certification up to ASIL-D by TÜV
SÜD planned
• IEC 61508 certification up to SIL-3 by TÜV
SÜD planned
• AEC-Q100 qualified on part number variants
ending in Q1
Device security (on select part numbers):
• Secure boot with secure run-time support
• Customer programmable root key, up to RSA-4K
or ECC-512
• Embedded hardware security module
• Crypto hardware accelerators – PKA with ECC,
AES, SHA, RNG, DES and 3DES
High speed serial interfaces:
• Integrated Ethernet switch supporting up to 8
external ports
– All ports support 2.5Gb SGMII
– All ports support 1Gb SGMII/RGMII
– All ports support 100Mb RMII
– Any two ports support QSGMII (using 4 internal
ports per QSGMII)
• Up to four PCI-Express® (PCIe) Gen3 controllers
– Up to two lanes per controller
– Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3
(8.0GT/s) operation with auto-negotiation
• Two USB 3.0 dual-role device (DRD) subsystem
– Two enhanced SuperSpeed Gen1 Ports
– Each port supports Type-C switching
– Each port independently configurable as USB
host, USB peripheral, or USB DRD
Automotive interfaces:
• Sixteen Modular Controller Area Network (MCAN)
modules with full CAN-FD support
• Two CSI2.0 4L RX plus One CSI2.0 4L TX
– 2.5Gbps RX throughput per lane (20Gbps total)
TDA4VM-Q1, TDA4VM
SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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