TDA4VM21 datasheet(12/331 Pages) TI

12 / 331 page

5.2 Pin Attributes

Note

MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT. BOOTMODE pins are latched on the rising edge of PORz_OUT.

Note

Media Local Bus (MLB) is not available on this device.The following balls must be left unconnected if not used in GPIO mode: AE2, AD2, AD3,

AC3, AC1, AD1

Note

PRU_ICSSG0 and PRU_ICSSG1 are not available on this device. The prg* signals should not be used. Those pins can be used for other

functions.

Note

Devices that support CPSW9G Gigabit Ethernet Interface of 4x RMII, 4x RGMII, 4x SGMII

Allowed instances and pins:

1. RMII1/RGMII1/SGMII1

2. RMII2/RGMII2/SGMII2

3. RMII3/RGMII3/SGMII3

4. RMII4/RGMII4/SGMII4

Devices that support CPSW9G Gigabit Ethernet Interface of 2x RMII, 2x RGMII, 2x SGMII

Allowed instances and pins:

1. RMII1/RGMII1/SGMII1

2. RMII2/RGMII2/SGMII2

Table 5-1. Pin Attributes

BALL NUMBER 1

BALL NAME 2

SIGNAL NAME 3

MUXMODE

TYPE 5

BALL

RESET

STATE 6

BALL

RESET

REL.

MUXMODE

I/O

VOLTAGE

VALUE 8

POWER 9

HYS 10

BUFFER

TYPE 11

PULL UP/

DOWN

TYPE 12

DSIS 13

RXACTIVE/

TXDISABL

E 14

CAP_VDDS0

CAP

K23

CAP_VDDS0_MCU

CAP

AB21

CAP_VDDS1

CAP

J18

CAP_VDDS1_MCU

CAP

Y18

CAP_VDDS2

CAP

J19

CAP_VDDS2_MCU

CAP

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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