TDA4VM21 datasheet(265/331 Pages) TI

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Table 6-77. MMC0 DLL Delay Mapping for All Timing Modes (continued)

MMCSD0_SS_PHY_CTRL_4_REG

MMCSD0_SS_PHY_CTRL_5_REG

BIT FIELD

[31:24]

[20]

[15:12]

[8]

[4:0]

[17:16]

[10:8]

[2:0]

BIT FIELD NAME

STRBSEL

OTAPDLYENA

OTAPDLYSEL

ITAPDLYENA

ITAPDLYSEL

SELDLYTXCLK

SELDLYRXCLK

FRQSEL

CLKBUFSEL

MODE

DESCRIPTION

STROBE

DELAY

OUTPUT

DELAY

ENABLE

OUTPUT

DELAY

VALUE

INPUT

DELAY

ENABLE

INPUT

DELAY

VALUE

DLL/

DELAY CHAIN

SELECT

DLL REF

FREQUENCY

DELAY

BUFFER

DURATION

High

Speed

DDR

8-bit PHY

operating 1.8 V,

50 MHz

0x0

0x1

0x5

0x1

0x3

0x0

0x4

0x7

HS200

8-bit PHY

operating 1.8 V,

200 MHz

0x0

0x1

0x6

0x1

Tuning

0x0

0x7

Table 6-78 presents timing conditions for MMC0.

Table 6-78. MMC0 Timing Conditions

PARAMETER

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

Legacy SDR

0.14

1.44

V/ns

High Speed SDR

0.3

0.9

V/ns

High Speed DDR (CMD)

0.3

0.9

V/ns

High Speed DDR (DAT[7:0])

0.45

0.9

V/ns

OUTPUT CONDITIONS

Output load capacitance

HS200

All other modes

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

All modes

126

756

td(Trace Mismatch

Delay)

Propagation delay mismatch across all

traces

Legacy SDR, High Speed SDR,

High Speed DDR

100

HS200

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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