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TDA4VM21 bảng dữ liệu(PDF) 252 Page - Texas Instruments |
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TDA4VM21 bảng dữ liệu(HTML) 252 Page - Texas Instruments |
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252 / 331 page ![]() 6.9.5.15 I3C For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. Table 6-60, Table 6-61 , Table 6-62, Figure 6-81, Table 6-64, Figure 6-82, and Figure 6-83 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-60. I3C Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.2276 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 50 pF Table 6-61. I3C Open Drain Timing Requirements see Figure 6-81 NO. MODE MIN MAX UNIT OD4 tsu(sdaV-sclH) Setup time, SDA valid before SCL rising edge Master 3 ns Table 6-62. I3C Open Drain Switching Characteristics see Figure 6-81 NO. PARAMETER MODE MIN MAX UNIT OD1 tw(sclL_od) Pulse duration, SCL low Master 200 ns tw(sclL_od_dig) tw(sclL_od) + tf(sda_od), min ns OD2 tw(sclH_od) Pulse duration, SCL high Master 41 ns tw(sclH_od_dig) tw(sclH_od) + tf(scl) ns OD3 tf(sda_od) Fall time, SDA Master tf(scl) 12 ns OD5 td(sclL-START) Delay time, SCL low after START (S) condition Master, ENTAS0 38.4 1000 ns Master, ENTAS1 38.4 100000 ns Master, ENTAS2 38.4 2000000 ns Master, ENTAS3 38.4 50000000 ns OD6 td(sclH-STOP) Delay time, SCL high before STOP (P) condition Master td(sclV), min / 2 ns OD7 tw(mmoverlap) Pulse duration, current master to secondary master overlap time during handoff Master tw(sclL_od_dig) ns OD8 tw(aval) Pulse duration, Bus Available condition Master 1000 ns OD9 tw(idle) Pulse duration, Bus Idle condition Master 1000000 ns OD10 tw(mmlock) Pulse duration, new master not driving SDA low Master tw(aval) ns TDA4VM-Q1, TDA4VM SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024 www.ti.com 252 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VM-Q1 TDA4VM |
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