TDA4VM21 datasheet(228/331 Pages) TI

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Table 6-56. GPIO Timing Conditions (continued)

PARAMETER

BUFFER TYPE

MIN

MAX UNIT

SRI

Input slew rate

LVCMOS

(VDD(1) = 1.8 V)

0.0018

6.6

V/ns

LVCMOS

(VDD(1) = 3.3V)

0.0033

6.6

V/ns

I2C OD FS

(VDD(1) = 1.8 V)

0.0018

6.6

V/ns

I2C OD FS

(VDD(1) = 3.3V)

0.0033

0.08

V/ns

OUTPUT CONDITIONS

Output load capacitance

LVCMOS

I2C OD FS

100

(1)

VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see

POWER column of the Pin Attributes table.

Section 6.9.5.11.1 and Section 6.9.5.11.2 present timings and switching characteristics of the GPIO Interface.

6.9.5.11.1 GPIO Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

GPIO1

tw(GPIO_IN)

Pulse width, GPIOn_x

2P + 30(1)

(1)

P = functional clock period in ns.

6.9.5.11.2 GPIO Switching Characteristics

NO.

PARAMETER

DESCRIPTION

BUFFER TYPE

MIN

MAX

UNIT

GPIO2 tw(GPIO_OUT)

Pulse width, GPIOn_x

LVCMOS

0.975P(1) -

3.6

I2C OD FS

160

(1)

P = functional clock period in ns.

For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.

6.9.5.12 GPMC

For more details about features and additional description information on the device General-Purpose Memory

Controller, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed

Description.

Table 6-57 represents GPMC timing conditions.

Note

The IO timings provided in this section are applicable for all combinations of signals for GPMC0.

However, the timings are only valid for GPMC0 if signals within a single IOSET are used. The IOSETs

are defined in the Section 6.9.5.12.4 , GPMC0_IOSET,table.

Table 6-57. GPMC Timing Conditions

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Input Conditions

tSR

Input slew rate

1.65

V/ns

Output Conditions

CLOAD

Output load capacitance

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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