LE58QL022BVC datasheet(45/61 Pages) ZARLINK

45 / 61 page

Le58QL022

Data Sheet

Zarlink Semiconductor Inc.

6C/6Dh Write/Read Interrupt Mask Register

R/W = 0: Write

R/W = 1: Read

Mask CD Interrupt

MCDxC = 0

CDxC bit is NOT MASKED

MCDxC = 1*

CDxC bit is MASKED

Bit number (A or B)

Channel number (1 through 4)

Masked: A change does not cause the Interrupt Pin to go Low.

This command does not depend on the state of the Channel Enable Register.

* Power Up and Hardware Reset (RST) Value = FFh.

70/71h Write/Read Operating Conditions

R/W = 0: Write

R/W = 1: Read

Cutoff Transmit Path

CTP = 0*

Transmit path connected

CTP = 1

Transmit path cut off

Cutoff Receive Path

CRP = 0*

Receive path connected

CRP = 1

Receive path cutoff (see note)

High Pass Filter

HPF = 0*

Transmit Highpass filter enabled

HPF = 1

Transmit Highpass filter disabled

Lower Receive Gain

LRG = 0*

6 dB loss not inserted

LRG = 1

6 dB loss inserted

Arm Transmit Interrupt

ATI = 0*

Transmit Interrupt not Armed

ATI = 1

Transmit Interrupt Armed

Interface Loopback

ILB = 0*

TSA loopback disabled

ILB = 1

TSA loopback enabled

Full Digital Loopback

FDL = 0*

Full digital loopback disabled

FDL = 1

Full digital loopback enabled

1 kHz Receive Tone

TON = 0*

1 kHz receive tone off

TON = 1

1 kHz receive tone on

* Power Up and Hardware Reset (RST) Value = 00h.

The B Filter is disabled during receive cutoff.

Command

0110110

R/W

I/O Data

MCDB4

MCDA4

MCDB3

MCDA3

MCDB2

MCDA2

MCDB1

MCDA1

Command

R/W

I/O Data

CTP

CRP

HPF

LRG

ATI

ILB

FDL

TON

LE58QL022BVC bảng dữ liệu(PDF) 45 Page - Zarlink Semiconductor Inc

LE58QL022BVC bảng dữ liệu(HTML) 45 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

bảng dữ liệu tải về

Link URL