LE58QL022BVC datasheet(43/61 Pages) ZARLINK

43 / 61 page

Le58QL022

Data Sheet

Zarlink Semiconductor Inc.

50/51h Write/Read AISN and Analog Gains

R/W = 0: Write

R/W = 1: Read

Disable Input Attenuator (GIN)

DGIN = 0*

Input attenuator off (DGIN = 1)

DGIN = 1

Input attenuator on (DGIN = 0)

Transmit Analog Gain

AX = 0*

0 dB gain

AX = 1

6.02 dB gain

Receive Analog Loss

AR = 0*

0 dB loss

AR = 1

6.02 dB loss

AISN coefficient

AISN = 0* – 31

See below (Default value = 0)

The Impedance Scaling Network (AISN) gain can be varied from

−0.9375 • GIN to +0.9375 • GIN in

multiples of 0.0625

• GIN.

The gain coefficient is decoded using the following equation:

where hAISN is the gain of the AISN. A value of AISN = 10000 turns on the Full Digital Loopback mode and

a value of AISN = 0000* indicates a gain of 0 (cutoff).

* Power Up and Hardware Reset (RST) Value = 00h.

52/53h Write/Read SLIC Input/Output Register

R/W = 0: Write

R/W = 1: Read

RSVD

Reserved for future use. Always write as 0, but 0 is not guaranteed when read.

Pins CD1, CD2, and C3 through C5 are set to 1 or 0. The data appears latched on the CD1, CD2, and C3 through C5 SLIC I/O

pins, provided they were set in the Output mode (see Command 54/55h on page page 43). The data sent to any of the pins set

to the Input mode is latched, but does not appear at the pins. The CD1B bit is only valid if the E1 Multiplex mode is enabled

(EE1 = 1).

* Power Up and Hardware Reset (RST) Value = 00h

54/55h Write/Read SLIC Input/Output Direction, Read Status Bits

R/W = 0: Write

R/W = 1: Read

RSVD

Reserved for future use. Always write as 0, but 0 is not guaranteed when read.

Channel Status (Read status only, write as 0)

Command

101000

R/W

I/O Data

DGIN

AISN4

AISN3

AISN2

AISN1

AISN0

Command

101001

R/W

I/O Data

RSVD

CD1B

CD2

CD1

Command

01010

R/W

Input Data

RSVD

CSTAT

CFAIL

IOD5

IOD4

IOD3

IOD2

IOD1

AISN

0.0625

GIN

•

AISN4

AISN3

AISN2

AISN1

AISN0

•

() 16

–

[]

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