SZF2002 datasheet(28/76 Pages) PHILIPS

28 / 76 page

1998 Aug 26

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontroller with

6-kbyte embedded RAM

SZF2002

15.4

Status of external pins

The status of the external pins during Idle and Power-down mode is shown in Table 20.

Table 20 Status of external pins during Idle and Power-down modes

15.5

Power Control Register (PCON)

Idle and Power-down modes are activated by software using this SFR. PCON is not bit addressed, the reset value of

PCON is 00000000B.

Table 21 Power Control Register (SFR address 87H)

Table 22 Description of PCON bits

MODE

MEMORY

PWM

PORTS 1, 3

AND 4

DATA BUS

Idle

internal

active

port data

Port 0 data

external

active

port data

ﬂoating

Power-down

internal

halted in last state

port data

Port 0 data

external

halted in last state

port data

ﬂoating

76543210

SMOD

ARD

RFI

WLE

GF1

GF0

IDL

BIT

SYMBOL

DESCRIPTION

SMOD

Double Baud rate. When set to a logic 1 the baud rate is doubled when the serial port

SIO0 is being used in modes 1, 2 or 3 (except when Timer 2 is used).

ARD

Setting this bit will force all MOVX instructions to access off-chip memory instead of

AUX RAM.

RFI

RFI reduction mode. Setting this bit will disable the ALE toggling during on-chip

memory access. The SZF2002 does not have this signal during operational mode, but

setting this bit will reduce the number of chip selects (CE) of the external memory (and

thus power).

WLE

Watchdog Load Enable. This ﬂag must be set by software prior to loading the

Watchdog Timer (T3). It is cleared when T3 is loaded.

GF1

General purpose ﬂag 1.

GF0

General purpose ﬂag 0.

1PD

Power-down mode selection. Setting this bit activates the Power-down mode. If a

logic 1 is written to both PD and IDL at the same time, PD takes precedence.

IDL

Idle mode selection. Setting this bit activates the Idle mode.

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