SZF2002 datasheet(66/76 Pages) PHILIPS

66 / 76 page

1998 Aug 26

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontroller with

6-kbyte embedded RAM

SZF2002

27 AC CHARACTERISTICS

Table 56 Timing with respect to CE, OE and WE

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

General (see Fig.29)

tXCLKH

XCLK HIGH time

31.25

−−

tXCLKL

XCLK LOW time

31.25

−−

Tcy(XCLK)

XCLK cycle time

62.5

−−

Memory Access (Figs 29 and 30)

t(CEL-OEL)1

CE LOW to OE LOW (data cycle)

−−

⁄2tCLK +3

t(OEL)1

OE LOW time (data cycle)

−−

⁄2tCLK +7

t(CEH-OEH)1

CE HIGH to OE HIGH (data cycle)

−

t(CEL)1

CE LOW time (data cycle)

−−

4tCLK

t(CEL-WEL)1

CE LOW to WE LOW (data cycle)

−−

⁄2tCLK +5

t(WEL)1

WE LOW time (data cycle)

−−

⁄2tCLK +8

t(CEH-WEH)1

CE HIGH to WE HIGH (data cycle)

−

tsu(OE-D)2

Data set-up time from OE (data read cycle)

−−

3tCLK − 18

tsu(CEL-D)2

Data set-up time from CE LOW (data read cycle)

−−

⁄2tCLK − 18 ns

tsu(D-WEL)3

Data set-up time to WE LOW (data write cycle)

−−

⁄2tCLK − 3ns

t(CEL-DV)3

Data valid time from CE LOW (data write cycle)

−−

3ns

tsu(D-SM)2

Data set-up time to sample moment (data read cycle); note 1

−−

8ns

th(SM-D)2

Data hold time from sample moment (data read cycle); note 1

−−

th(WEH-D)3

Data hold time from WE HIGH (data write cycle)

−−

tCLK − 20

th(CEH-D)3

Data hold time from CE HIGH (data write cycle)

−−

tCLK − 10

tsu(A-CEL)1

Address set-up time to CE LOW (data cycle)

−−

⁄2tCLK − 5ns

th(CEH-A)1

Address hold time from CE HIGH (data cycle)

−−

tCLK

t(CEL-OEL)4

CE LOW to OE LOW (code fetch cycle)

−−

⁄2tCLK

t(OEL)4

OE LOW time (code fetch cycle)

−−

⁄2tCLK

t(CEH-OEH)4

CE HIGH to OE HIGH (code fetch cycle)

−

2ns

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