SZF2002 datasheet(67/76 Pages) PHILIPS

67 / 76 page

1998 Aug 26

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontroller with

6-kbyte embedded RAM

SZF2002

Notes

1. Sample moment for data read cycles is on negative clock edge in state S3, the internal clock skew must be taken

into account also. This results in 3tCLK − 10 ns from OE LOW (or 7⁄2tCLK − 10 ns from CE LOW) maximum.

2. Sample moment for code fetch cycles is on negative clock edge in state S2 or S4, the internal clock skew must be

taken into account also. This results in 3

⁄2tCLK − 10 ns from OE LOW (or 2tCLK − 10 ns from CE LOW) maximum.

t(CEL)4

CE LOW time (code fetch cycle)

−−

2tCLK

tsu(OE-D)4

Data set-up time from OE (code fetch cycle)

−−

⁄2tCLK − 18 ns

tsu(CEL-D)4

Data set-up time from CE LOW (code fetch cycle)

−−

2tCLK − 18

tsu(D-SM)4

Data set-up time to sample moment (code fetch cycle), note 2

−−

8ns

th(SM-D)4

Data hold time from sample moment (code fetch cycle)

−−

tsu(DZ-OEL)

Data bus high-impedance set-up time to OE LOW

(data read cycle); (Code Fetch cycle)

⁄2tCLK +12 −−

th(DZ-OEH)

Data bus high-impedance hold time from OE HIGH

(data read cycle); (code fetch cycle)

⁄2tCLK − 2;

tCLK − 11

−−

tsu(A-CEL)4

Address set-up time to CE LOW (code fetch cycle)

−−

⁄2tCLK − 4ns

th(CEH-A)4

Address hold time from CE HIGH (code fetch cycle)

−−

⁄2tCLK

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

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