SZF2002 datasheet(69/76 Pages) PHILIPS

69 / 76 page

1998 Aug 26

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontroller with

6-kbyte embedded RAM

SZF2002

Table 57 Timing ﬁgures with respect to RAMCE, OE and WEL

Notes

1. Sample moment for data read cycles is on negative clock edge in state S3, the internal clock skew must be taken

into account also. This results in 3tCLK − 10 ns from OE LOW (or 7⁄2tCLK − 10 ns from RAMCE LOW) maximum.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

General (see Fig.29)

tXCLKH

XCLK HIGH time

31.25

−−

tXCLKL

XCLK LOW time

31.25

−−

Tcy(XCLK)

XCLK cycle time

62.5

−−

Memory Access (Figs 29 and 30)

t(RCEL-OEL)

RAMCE LOW to OE LOW

−−

⁄2tCLK − 3ns

t(OEL)

OE LOW time

−−

⁄2tCLK +8

t(RCEH-OEH)

RAMCE HIGH to OE HIGH

−

6ns

t(RCEL)

RAMCE LOW time

−−

4tCLK − 1ns

t(RCEL-WEL)

RAMCE LOW to WE LOW

−−

⁄2tCLK − 2ns

t(WEL)

WE LOW time

−−

⁄2tCLK +7

t(RCEH-WEH)

RAMCE HIGH to WE HIGH

−

7ns

tsu(OEL-D)

Data set-up time from OE LOW

−−

3tCLK − 18

tsu(RCEL-D)

Data set-up time from RAMCE LOW

−−

⁄2tCLK − 20 ns

tsu(D-WEL)

Data set-up time to WE LOW

−−

⁄2tCLK +3

t(RCEL-DV)

Data valid time from RAMCE LOW

−−

4ns

tsu(D-SM)

Data set-up time to sample moment, note 1

−−

8ns

th(SM-D)

Data hold time from sample moment; note 1

−−

th(WEH-D)

Data hold time from WE HIGH

−−

tCLK − 7ns

th(RCEH-D)

Data hold time from RAMCE HIGH

−−

tCLK − 14

tsu(A-RCEL)

Address set-up time to RAMCE LOW

−−

⁄2tCLK

th(RCEH-A)

Address hold time from RAMCE HIGH

−−

tCLK − 7ns

tsu(DZ-OEL)

Data bus high-impedance set-up time to OE LOW

⁄2tCLK +1

−−

th(OEH-DZ)

Data bus high-impedance hold time from OE HIGH

⁄2tCLK − 10 −−

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