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H-PLL and Clamp Control

Sync-On-Green Threshold

TVP7002

SLES206 – MAY 2007

Subaddress

0Fh

Default (2Eh)

7

6

5

4

3

2

1

0

CF

CP

Coast Sel

CPO

CPC

SMO

FCPD

ADC Test

Clamp Function: Clamp pulse select. This control bit determines whether the timing for both the fine clamp and the ALC circuit are

generated internally or externally.

0 = Internal fine clamp and ALC timing (default)

1 = External fine clamp and ALC timing (pin 76)

Clamp Polarity: External clamp polarity select

0 = Active high clamp pulse (default)

1 = Active low clamp pulse

Coast Select: Coast signal select. This control bit determines whether the timing for H-PLL coast signal is generated internally or externally.

0 = External H-PLL coast timing (pin 77)

1 = Internal H-PLL coast timing (default)

Coast Polarity Override:

0 = Polarity determined by chip (default)

1 = Polarity set be Bit 3 in register 0Fh

Coast Polarity Change: External coast polarity select

0 = Active low coast signal

1 = Active high coast signal (default)

Seek Mode Override: Places the TVP7002 in a low power mode whenever no activity is detected on the selected sync inputs.

0 = Enable automatic power management mode

1 = Disable automatic power management mode (default)

Note: Digital outputs are not high impedance and may be in a random state during low power mode. Outputs can be put in

0 = Power-down mode

1 = Normal operation (default)

Note: Digital outputs are not high impedance and may be in random state during FCPD. Outputs can be put in high

ADC Test: Active high ADC test mode select. When placed in the ADC test mode, the TVP7002 disables the fine clamp, enables the coarse

clamp, and selects the external clock input (pin 80) for each ADC channel.

0 = ADC test mode disabled (default)

1 = ADC test mode enabled

Note: Also see the Horizontal PLL Control register at subaddress 03h.

Subaddress

10h

Default (5Dh)

7

6

5

4

3

2

1

0

SOG Threshold [4:0]

Blue CS

Green CS

Red CS

SOG Threshold [4:0]: Sets the voltage level of the SOG slicer comparator according to the following equation.

slice_level = (350 mV)

× (N

00h = 0 mV

0Bh = 124 mV (default)

1Fh = 350 mV

Blue Clamp Select: This bit has no effect when the Blue channel fine clamp is disabled (bit 2 of subaddress 2Ah).

0 = Bottom-level fine clamp

1 = Mid-level fine clamp (default)

Green Clamp Select: This bit has no effect when the Green channel fine clamp is disabled (bit 1 of subaddress 2Ah).

0 = Bottom-level fine clamp (default)

1 = Mid level fine clamp

Red Clamp Select: This bit has no effect when the Red channel fine clamp is disabled (bit 0 of subaddress 2Ah).

0 = Bottom-level fine clamp

1 = Mid-level fine clamp (default)

Note: Bottom-level clamping is required for Y and RGB inputs, while mid-level clamping is required for Pb and Pr inputs. The internal clamp

pulse must also be correctly positioned for proper clamp operation. See register 05h.

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