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TVP7002PZP bảng dữ liệu(PDF) 27 Page - Texas Instruments

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tên linh kiện TVP7002PZP
Giải thích chi tiết về linh kiện  TRIPLE 8-/10-BIT 165-/110-MSPS, VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL
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TVP7002PZP bảng dữ liệu(HTML) 27 Page - Texas Instruments

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H-PLL Phase Select
Clamp Start
Clamp Width
HSYNC Output Width
Blue Fine Gain
TVP7002
SLES206 – MAY 2007
Subaddress
04h
Default (80h)
7
6
5
4
3
2
1
0
Phase Select [4:0]
Reserved
DIV2
Phase Select [4:0]: ADC sampling clock phase select. (1 LSB = 360/32 = 11.25
°). A host-based automatic phase control algorithm can be
used to control this setting to optimize graphics sampling phase.
00h = 0 degrees
10h = 180 degrees (default)
1Fh = 348.75 degrees
DIV2: DATACLK Divide-by-2. H-PLL post divider (internal use only)
0 = DATACLK/1 (default)
1 = DATACLK/2
Note: Phase wrap-around and phase instability can occur with phase settings of 00h or 01h. These settings are therfore not recommended
for use. Not all 32 phase settings are available when using the DATACLK/2 setting. This setting is therefore not recommended for PC
graphics inputs.
Subaddress
05h
Default (32h)
7
6
5
4
3
2
1
0
Clamp Start [7:0]
Clamp Start [7:0]: Positions the clamp signal an integer number of clock periods after the HSYNC signal. If external clamping is selected
this value has no meaning. Clamp Start must be correctly positioned for proper operation. See Table 10 for the recommended settings.
Subaddress
06h
Default (20h)
7
6
5
4
3
2
1
0
Clamp Width [7:0]
Clamp Width [7:0]: Sets the width in pixels for the fine clamp. See also register Clamp Start (subaddress 05h).
Table 10. Recommended Fine Clamp Settings
VIDEO STANDARD
CLAMP START
CLAMP WIDTH
HDTV (tri-level)
50 (32h)
32 (20h)
SDTV (bi-level)
6 (06h)
16 (10h)
PC Graphics
6 (06h)
16 (10h)
Subaddress
07h
Default (20h)
7
6
5
4
3
2
1
0
HSOUT Width [7:0]
HSOUT Width [7:0]: Sets the width in pixels for HSYNC output.
Subaddress
08h
Default (00h)
7
6
5
4
3
2
1
0
Blue Fine Gain [7:0]
Blue Fine Gain [7:0]: 8-bit fine digital gain (contrast) for Blue channel (applied after the ADC). Offset binary value.
Blue Fine Gain = 1 + Blue Fine Gain [7:0]/256
Blue Fine Gain [7:0]
Blue Fine Gain
00h
1.0 (default)
80h
1.5
FFh
2.0
27
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