TVP7002PZP datasheet(17/52 Pages) TI

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Sync Slicer

Sync Separator

Sync Activity Detection (Informative)

TVP7002

SLES206 – MAY 2007

TVP7002 includes a circuit that compares the input signal on Green channel to a level 150 mV (typical value)

above the clamped level (sync tip). The slicing level is programmable by I2C register subaddress at 10h. The

digital output of the composite sync slicer is available on the SOGOUT pin.

Noise Immunity

In general, noise on a slowly varying input signal (i.e., sync falling edge) may cause a voltage comparator to

false trigger as the input passes through the linear range of the comparator. To improve the overall performance

of the TVP7002 sync slicer in the presence of noise on the SOG input, the voltage comparator includes

hysteresis. Maintaining a 50% slice level using the I2C programmable slice level control can further improve the

noise immunity of the Sync slicer. The slice level is programmable in 11.2-mV increments over a 350-mV range

as follows.

slice_level = (350 mV)

× (N

TH/31)

where 0

≤ N

TH ≤ 31, default: 11

≤ slice_level ≤ 350 mV

Glitch Immunity

During white to black transitions, the input video waveform may undershoot below the sync slicer threshold. To

help attenuate the amplitude of such glitches, a single-pole low-pass filter with three selectable cutoff

frequencies (2.5, 10, and 33 MHz) is provided at the input of the SOG voltage comparator circuit. This filter is

bypassed in the default mode.

NOTE:

Although the low-pass filter may attenuate the amplitude of glitches present on the

SOG input, it also makes the sync falling edge less sharp.

The sync separator automatically extracts VSYNC and HSYNC from the sliced composite sync input supplied at

the SOG input. The G or Y input containing the composite sync must be ac coupled to the SOG input pin using

a 1-nF capacitor. Support for PC graphics, SDTV, EDTV, and HDTV up to 1080p is provided.

The TVP7002 provides activity detection on the sync inputs (VSYNC, HSYNC) to enable the host processor to

determine whether the PC graphics source is configured as a 3-wire, 4-wire, or 5-wire interface as defined here:

• 5 wire (G, B, R, HSYNC, VSYNC)

• 4 wire (G, B, R, CSYNC)

• 3 wire (G, B, R with SOG)

If activity is detected on the VSYNC input, the host processor should assume that the PC graphics input is

configured as a standard 5-wire interface. In this case, the HSYNC input of the TVP7002 should be configured

as an HSYNC input.

If activity is detected on the HSYNC input but not on the VSYNC input, the host processor should assume that

the PC graphics input is configured as a standard 4-wire interface. In this case, the HSYNC input of the

TVP7002 should be configured as a CSYNC input. The TVP7002 supports the following two types of CSYNC

inputs.

CSYNC = VSYNC XOR HSYNC (default)

CSYNC = VSYNC OR HSYNC

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