DSP56F802 datasheet(24/40 Pages) FREESCALE

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56F802 Technical Data, Rev. 9

Freescale Semiconductor

Figure 3-8 Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC

3.5.2

Phase Locked Loop Timing

Table 3-9 PLL Timing

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency for the PLL1

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 8MHz input crystal.

2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the

User Manual. ZCLK = fop

Will not exceed 60MHz for the DSP56F802TA60 device.

4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.

fosc

MHz

PLL output frequency2

fout/2

—

803

MHz

PLL stabilization time4 0o to +85oC

tplls

—

PLL stabilization time4 -40o to 0oC

tplls

—

100

200

10 20 30 4050 60 7080 90 A0 B0 C0 D0 E0 F0

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