AVR32AP datasheet(52/181 Pages) ATMEL

52 / 181 page

32001A–AVR32–06/06

AVR32

Figure 4-3.

The MMU interface registers

4.2.2.1

TLB Entry Register High Part - TLBEHI

The content of the TLBEHI and TLBELO registers is loaded into the TLB when the tlbw instruc-

tion is executed. The TLBEHI register consists of the following fields:

• VPN - Virtual Page Number in the TLB entry. This field contains 22 bits, but the number of

bits used depends on the page size. A page size of 1 Kb requires 22 bits, while larger page

sizes require fewer bits. When preparing to write an entry into the TLB, the virtual page

number of the entry to write should be written into VPN. When an MMU-related exception has

occurred, the virtual page number of the failing address is written to VPN by hardware.

• V - Valid. Set if the TLB entry is valid, cleared otherwise. This bit is written to 0 by a reset. If

an access to a page which is marked as invalid is attempted, an TLB Miss exception is

raised. Valid is set automatically by hardware whenever an MMU exception occurs.

• I - Instruction TLB. The I bit is set by hardware when an MMU-related exception occurs,

indicating whether the error was caused by instructions or data. All MMU operations always

use the unified TLB no matter which state the I bit is in.

• ASID - Application Space Identifier. The operating system allocates a unique ASID to each

process. This ASID is written into TLBEHI by the OS, and used in the TLB address match if

the MMU is running in Private Virtual Memory mode and the G bit of the TLB entry is cleared.

ASID is never changed by hardware.

VPN

ASID

TLBEHI

PFN

TLBELO

8 765 43 2 1

PTBR

TLBEAR

DLA

MMUCR

DRP

TLBARLO

AVR32AP bảng dữ liệu(PDF) 52 Page - ATMEL Corporation