AVR32AP datasheet(42/181 Pages) ATMEL

42 / 181 page

32001A–AVR32–06/06

AVR32

3.11.1.20

DTLB Read Miss Exception

The DTLB Read Miss exception is generated when no TLB entry matches the data memory

address of the current read operation, or if the Valid bit in a matching entry is 0.

RSR_EX = SR;

RAR_EX = PC;

TLBEAR = FAILING_VIRTUAL_ADDRESS;

TLBEHI[VPN] = FAILING_PAGE_NUMBER;

TLBEHI[I] = 0;

SR[R] = 0;

SR[J] = 0;

SR[M2:M0] = B’110;

SR[EM] = 1;

SR[GM] = 1;

PC = EVBA | 0x60;

3.11.1.21

DTLB Write Miss Exception

The DTLB Write Miss exception is generated when no TLB entry matches the data memory

address of the current write operation, or if the Valid bit in a matching entry is 0.

RSR_EX = SR;

RAR_EX = PC;

TLBEAR = FAILING_VIRTUAL_ADDRESS;

TLBEHI[VPN] = FAILING_PAGE_NUMBER;

TLBEHI[I] = 0;

SR[R] = 0;

SR[J] = 0;

SR[M2:M0] = B’110;

SR[EM] = 1;

SR[GM] = 1;

PC = EVBA | 0x70;

3.11.1.22

DTLB Read Protection Exception

The DTLB Protection exception is generated when the data memory read violates the access

rights specified by the protection bits of the addressed virtual page.

RSR_EX = SR;

RAR_EX = PC;

TLBEAR = FAILING_VIRTUAL_ADDRESS;

TLBEHI[VPN] = FAILING_PAGE_NUMBER;

TLBEHI[I] = 0;

SR[R] = 0;

SR[J] = 0;

SR[M2:M0] = B’110;

SR[EM] = 1;

SR[GM] = 1;

PC = EVBA | 0x3C;

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