AVR32AP datasheet(69/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

Instruction Cache

The AVR32 AP uses an instruction cache in order to increase performance and lower power

consumption. The cache has the following features:

• Virtually indexed, physically tagged.

• 4-way Set-associative.

• 32-byte line size.

• Least recently used (LRU) allocate-on-read-miss line replacements.

• Easily portable using standard single and two port RAMs.

• Lockable on a per-line basis.

• Cacheable or uncacheable operation configurable on a per-page basis through the MMU.

• All accesses are subject to MMU protection and translation checks.

• Powerful cache maintenance operations, allowing many common cache operations to be

performed through a single instruction.

The number of sets in the instruction cache is specified in the CONFIG1 register described in

chapter 2.6. The total cache size is (number of sets * line size * associativity), i.e. (128 * number

of sets) bytes.

6.1

Behaviour

Reset invalidates all entries in the ICache.

All instruction fetches will result in an ICache lookup and will return the cached data if the

requested address is found in the cache (a cache hit). If data are found in the cache, they are

returned even if the memory area is marked as uncacheable. If the address is not found (a

cache miss) and the address is in a cacheable area, a burst read access is started on the sys-

tem bus in order to read an entire cache line of data. The read data will be written to an unlocked

line according to a LRU scheme, possibly replacing another line.

If a cache miss is in an uncacheable area, a single non-sequential read is started on the system

bus.

If the MMU is disabled or the fetch is from an unmapped segment, the cacheability of memory

areas is predefined as shown in the architecture manual. If the MMU is enabled and the fetch is

from a mapped segment, the cacheability of memory areas is controlled through the C bit in the

TLB.

If the MMU signals an exception, the cache will abandon the fetch. The exception is handled by

the CPU as soon as it knows if the instruction should really be executed, but is ignored if it turns

out to be a needlessly prefetched instruction.

There is no hardware support for self-modifying code. If any memory that may be cached in the

ICache is modified during execution, the programmer is responsible for ensuring ICache consis-

tency. See chapter 6.3 for details on how to do this.

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